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A.2. AMBA AHB slave interface signals

Table A.2 describes the AMBA AHB slave interface signals.

AMBA AHB slave interface signals

Signal name

Type

Source/ destination

Description

HADDR[28:0]

Input

AMBA AHB master

System address bus, least significant 29 bits, driven by the active bus master.

HTRANS[1:0]

Input

AMBA AHB master

Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HWRITE

Input

AMBA AHB master

Transfer direction signal. When HIGH, this signal indicates a write to the SMC and when LOW, a read from the SMC block.

HSIZE[2:0]

Input

AMBA AHB master

Transfer size signal. This signal indicates the size of the current transfer, which can be byte (8-bit), halfword (16-bit), or word (32-bit).

HBURST[2:0]

Input

AMBA AHB master

Indicates if the transfer forms part of a burst. Four, eight, and 16 beat bursts are supported and the burst can either be incrementing or wrapping.

HWDATA[31:0]

Input

AMBA AHB master

Write data bus, used to transfer data to this block.

HSELSMC

Input

AMBA AHB decoder

Slave select signal for SMC memory banks.

HSELREG

Input

AMBA AHB decoder

Slave select signal for SMC SMBCRx and SMBSRx Registers.

HRDATA[31:0]

Output

AMBA AHB slave

Read data bus, used to read data from this block.

HREADYOUT

Output

AMBA AHB slave

Transfer done output. When HIGH indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESP[1:0]

Output

AMBA AHB slave

The transfer response provides additional information on the status of a transfer. Two different responses are provided, OKAY and ERROR.

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