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A.5. Input/output pad signals

Table A.5 describes the signals to the input/output pads.

Input/output pad signals

Signal name

Type

Source/ destination

Description

SMMWCS7[1:0]

Input

Input pad

These static configuration bits indicate the memory width used for boot memory bank seven:

00 = 8-bit

01 = 16-bit

10 = 32-bit

11 = no change.

SMWAIT

Input

Input pad

Wait mode input from external memory controller. Active HIGH, or active LOW, (default), as programmed in the SMC Control Registers for each bank.

CANCELSMWAIT

Input

Input pad

This signal enables the system to recover from an externally waited transfer that takes longer than expected to finish. Active HIGH.

SMDATAIN[31:0]

Input

Input pad

External input data bus used to read data from memory bank.

SMDATAOUT[31:0]

Input

Input pad

External output data used to write data from SMC to memory bank.

SMRBLECS7InputInput pad

This static configuration bit indicates the memory device read byte lane setting used for boot memory bank seven:

0 = 8-bit, or devices using the byte lane enable as write enable.

1 = 16 or 32-bit, or devices with separate byte lane and write enable inputs.

SMADDR[25:0]

Output

Output pad

External memory address bus, to external memory banks.

SMCS[7:0]

Output

Output pad

Chip select for external memory banks 7-0, default active LOW.

nSMDATAEN[3:0]

Output

Output pad

Tristate input/output pad enable for the byte lanes of the external memory data bus SMDATA[31:0], active LOW. Enables the byte lanes [31:24], [23:16], [15:8], and [7:0] of the data bus independently.

nSMWEN

Output

Output pad

Write enable for the external memory banks, active LOW.

nSMBLS[3:0]

Output

Output pad

Byte lane select signals, active LOW. The signals nSMBLS[3:0] select byte lanes [31:24], [23:16], [15:8], [7:0] on the data bus.

nSMOEN

Output

Output pad

Output enable for external memory banks, active LOW.

TESTREQA

Input

Input pad

This is the Test Bus Request A input signal and is required as a dedicated device pin.

During normal system operation the TESTREQA signal is used to request entry into the test mode. During test TESTREQA is used, in combination with TESTREQB, to indicate the type of test vector that is applied in the following cycle.

TESTREQB

Input

Input pad

During test this signal is used, in combination with TESTREQA, to indicate the type of test vector that is to be applied in the following cycle.

TESTACK

Output

Output pad

The test bus acknowledge signal gives external indication that the TIC is granted and also indicates when a test access is complete. When TESTACK is LOW, the current test vector must be extended until TESTACK becomes HIGH.

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