The SMC can be configured for each memory bank to use external bus turnaround cycles between read and write memory accesses. The IDCY field can be programmed for up to 15 bus turnaround wait states. This is to avoid bus contention on the external memory data bus. Bus turnaround cycles are generated between external bus transfers as follows:
read-to-read, to different memory banks
read-to-write, to the same memory bank
read-to-write, to different memory banks.
Figure 2.18 shows the timing diagram for a zero wait read followed by a zero wait write with default turnaround between the transfers of two cycles because of the timing of the AHB transfers. Standard AHB wait states are added to the transfers, two for the read, and zero for the write.
Figure 2.19 shows the timing diagram for a zero wait write followed by a zero wait read with default turnaround between the transfers of one cycle. No AHB wait states are added to the write transfer, but four are added to the read, two to enable the write to complete before the read is started, and then the standard two for the read transfer.
Figure 2.20 shows the timing diagram for zero wait read followed by two zero wait writes with two turnaround cycles added. The standard minimum of two AHB wait states are added to the read transfer, and none are added to the first write (as for any read-write transfer sequence). Two AHB wait states are added to the second write because of insertion of the two turnaround cycles that are only generated after the first write transfer is detected.