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2.9. Byte lane control

The SMC generates byte lane control signals nSMBLS[3:0] according to:

  • little or big-endian operation

  • AMBA transfer width (indicated by HSIZE[2:0])

  • external memory bank data bus width, defined within each SMBCRx Register

  • external memory bank type, being either byte, halfword or word

  • the decoded HADDR[1:0] value for write accesses only.

Word transfers are the largest size transfers supported by the SMC. Any access attempted with a size greater than a word generates the error response.

Each memory bank can either be 8, 16, or 32 bits wide. The memory configuration for a particular memory bank determines how the nSMWEN and nSMBLS signals are connected to provide byte, halfword, and word access. For read accesses, it is necessary to control the nSMBLS signals by driving them either all HIGH, or all LOW.

This control is achieved by programming the RBLE bit in each SMBCRx Register. The following two sections explain why different connections in respect of nSMWEN and nSMBLS[3:0] are required for different memory configurations.

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