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2.12. Data bus interface operation

The Data Bus Interface (DBI) enables both parts of the SMC and the additional memory controller to share the external address and data buses, by only selecting one device to drive them at a time. The following lines are multiplexed by this block:

  • SMADDR/MCADDR

  • SMDATAOUT/TBUSOUTEBI/MCDATAOUT

  • nSMDATAEN/TICREADEBI/MCDATAEN.

All other signals pass directly to the memory controllers and the test controller, including the external data input.

A simple priority-based request and grant system is used, with the TIC the highest priority device (because it must always be possible to enter test mode), and the PrimeCell SMC the lowest priority device. The bus interface degrants a lower priority device when a higher priority device requests control of the bus, but the higher priority device only gains control of the bus when the lower priority device finishes the current transfer and releases control of the bus. The SMC is granted control of the bus by default, reducing the access time during normal operation.

An example of the timing of the bus interface is shown in Figure 2.33.

Figure 2.33. Example of bus interface timing

Figure 2.33. Example of bus interface timing

When the SMC requests the bus the other higher priority device is not requesting control of the bus (MCBUSREQ deasserted), so the SMC is granted immediately. However, during the course of the SMC transfer, the higher priority device requests the bus (MCBUSREQ asserted) and hence the SMC grant line is taken LOW by the DBI in the following cycle. This indicates to the SMC that it must complete the current external transfer and deassert SMBUSREQ. When the SMC has reached the end of this transfer it sets the SMBUSREQ output LOW, that indicates to the DBI that it can grant control of the external bus to the other higher priority device. If the SMC still has further transfers to complete, for example it might have terminated a word access from a byte-wide memory after two bytes, then it can reassert the SMBUSREQ signal one clock cycle after deasserting it and wait to be regranted before continuing the transfer.

The timing in Figure 2.33 shows the minimum time it takes for the additional memory controller to gain control of the bus if the SMC is currently granted and performing a transfer. The additional controller must wait a minimum of two cycles between asserting its bus request and the DBI asserting the bus grant. It takes one cycle for the SMC to be degranted, and a minimum of one cycle for the SMC to deassert its bus request output and for the additional controller to gain control of the bus. The maximum time that can occur before gaining control of the external bus depends on the system, because an externally waited SMC transfer has no time limit, and depends on the device driving CANCELSMWAIT to set a maximum time limit for a waited transfer.

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