The SMC supports the extension of the access cycle by an external device like a memory controller by using the SMWAIT input pin of the PrimeCell SMC. For this, the WaitEn bit of the SMBCRx register must be programmed appropriately. The polarity of the external SMWAIT input is programmed through the WaitPol field of the SMBCRx Register. If a problem occurs the active HIGH CANCELSMWAIT input enables externally waited transfers to be terminated early.
Because the external wait control inputs (SMWAIT and CANCELSMWAIT) are asynchronous inputs, they are synchronized before use. This gives all operations using external waits a two cycle delay because of the synchronization time. Only single transfers might be performed using the external wait control. Burst transfers controlled by the external wait are not supported, and might result in unpredictable behavior.
When external wait mode is enabled, the SMC checks for assertion of the SMWAIT input, and waits the current transfer while SMWAIT stays asserted. The transaction completes when the SMWAIT line is deasserted (taking into account the two-cycle synchronization delay).
If the external wait control mode is disabled, then the SMC ignores the SMWAIT input and the access time is generated normally according to the values programmed in the SMBWST1Rx and SMBWST2Rx Registers.