Eight independently configurable memory banks are supported, with a separate chip select output for each bank. The chip select lines SMCS[7:0] for all banks are configurable to be either active HIGH or active LOW (default). Table 2.1 shows how memory bank selection is controlled by the AMBA AHB address lines HADDR[28:26]. All SMCS lines are shown as active HIGH.
The base addresses of the external memory banks and the PrimeCell
SMC memory bank registers are defined in the AMBA AHB address decoder.
This generates the AHB slave select signals HSELSMC and HSELREG. If the default base address
of the external memory banks begins at
the memory banks occupy address space up to
Table 2.2 shows the address mapping of HADDR[31:0] for external memory banks and for memory bank Configuration Registers.
|External memory banks|
Base address for PrimeCell SMC memory
Chip select address space for eight memory banks
64MB memory banks address space
|Memory bank Configuration Registers||Base address for PrimeCell AHB SMC registers||Unused||Unused|
Memory bank register select
 HADDR[31:29] are not inputs to the SMC. Decoding is performed in the AMBA address decoder.