The SMC is designed to enable the use of an external bus multiplexor, instead of the internal DBI, to control the switching of the external data and address buses, for example if the SMC is to be used with an SDRAM controller that requires a bus multiplexor that can handle the necessary synchronization retiming.
The EXTBUSMUX input must be tied HIGH so that the internal DBI is bypassed and the external bus multiplexor is used instead. This enables the external request and grant ports instead of the internal DBI connections.
If the external bus multiplexor contains retiming registers on the address output path, for example when used with a synchronous memory controller such as an SDRAM controller, ensure that the WSTWEN values for all writable register banks are set to a minimum of one, and that the WST2 values are also set to a minimum of one for the same banks. This is because the write enable must only be valid after the address output is stable to make sure that the write is to the correct address. This is only required for writes because of the half a clock cycle timing between the address being stable and the write enable being asserted. Because reads use full cycle timing, no special settings are required.
The SMC and TIC bus request and grant ports must be connected to the external bus multiplexor, ensuring that if the TIC is used it is connected to the ports for the highest priority device because it must always be able to enter test mode. The SMC address, data, and data enable ports and the TIC data and data enable ports must also be connected.
The additional memory controller ports of the SMC are not used when the internal DBI is bypassed. Any additional controller must be connected directly to the external bus multiplexor. When the SMC is used with an SDRAM controller, care must be taken to ensure that the SMC does not take control of the bus for longer than the refresh timing of the SDRAM. Because externally waited transfers have undefined lengths, the system must be able to use the CANCELSMWAIT signal to cancel any externally waited transfer and enable the SDRAM refresh to occur.