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1.6.1. Section 2.8.1 SMWAIT assertion timing

In the wait enabled or external wait control mode, when the SMC is waiting for the SMWAIT assertion, it also starts counting down according to the values programmed in the wait state count field WST1 or WST2, that are used for read and write transfers respectively. You can use this feature to ensure that adequate time is available to the SMC to detect SMWAIT as there might be a delay before the external device asserts SMWAIT. If SMWAIT is not asserted during this time, the transfer is assumed to be zero wait.


When you use the SMWAIT input to time memory transfers, the WST1 and WST2 timing registers are used to program the external wait assertion delay. You must set these registers to a minimum of 0x03 instead of the default of 0x00 for standard memory transfers:

  • One cycle is required for the minimum chip select to external wait assertion delay

  • Two cycles are required for the double synchronization of the SMWAIT input before use.

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