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3.2. Summary of registers

All register addresses in the SMC are fixed relative to the SMC base address. Table 3.1 lists the registers in base offset order.

PrimeCell SMC read/write register summary

Register

Offset from base

Type

Reset value

Function

SMBIDCYR0

0x00

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R0

0x04

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R0

0x08

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR0

0x0C

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR0

0x10

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR0

0x14

RW

0x80

See Bank Control Registers 0-7

SMBSR0

0x18

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR1

0x1C

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R1

0x20

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R1

0x24

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR1

0x28

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR1

0x2C

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR1

0x30

RW

0x00

See Bank Control Registers 0-7

SMBSR1

0x34

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR2

0x38

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R2

0x3C

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R2

0x40

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR2

0x44

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR2

0x48

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR2

0x4C

RW

0x40

See Bank Control Registers 0-7

SMBSR2

0x50

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR3

0x54

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R3

0x58

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R3

0x5C

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR3

0x60

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR3

0x64

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR3

0x68

RW

0x00

See Bank Control Registers 0-7

SMBSR3

0x6C

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR4

0x70

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R4

0x74

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R4

0x78

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR4

0x7C

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR4

0x80

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR4

0x84

RW

0x80

See Bank Control Registers 0-7

SMBSR4

0x88

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR5

0x8C

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R5

0x90

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R5

0x94

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR5

0x98

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR5

0x9C

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR5

0xA0

RW

0x80

See Bank Control Registers 0-7

SMBSR5

0xA4

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR6

0xA8

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R6

0xAC

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R6

0xB0

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR6

0xB4

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR6

0xB8

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR6

0xBC

RW

0x40

See Bank Control Registers 0-7

SMBSR6

0xC0

RW

0x0

See Bank Status Registers 0-7

SMBIDCYR7

0xC4

RW

0xF

See Bank Idle Cycle Control Registers 0-7

SMBWST1R7

0xC8

RW

0x1F

See Bank Wait State 1 Control Registers 0-7

SMBWST2R7

0xCC

RW

0x1F

See Bank Wait State 2 Control Registers 0-7

SMBWSTOENR7

0xD0

RW

0x0

See Bank Output Enable Assertion Delay Control Registers 0-7.

SMBWSTWENR7

0xD4

RW

0x1

See Bank Write Enable Assertion Delay Control Registers 0-7

SMBCR7

0xD8

RW

0x00

See Bank Control Registers 0-7

SMBSR7

0xDC

RW

0x0

See Bank Status Registers 0-7

SMBEWS

0xE0

RO

0x0

See External Wait Status Register

SMCPeriphID0

0xFE0

RO

0x92

See Peripheral Identification Register 0

SMCPeriphID1

0xFE4

RO

0x10

See Peripheral Identification Register 1

SMCPeriphID2

0xFE8

RO

0x04

See Peripheral Identification Register 2

SMCPeriphID3

0xFEC

RO

0x00

See Peripheral Identification Register 3

SMCPCellID0

0xFF0

RO

0x0D

See PrimeCell Identification Register 0

SMCPCellID1

0xFF4

RO

0xF0

See PrimeCell Identification Register 1

SMCPCellID2

0xFF8

RO

0x05

See PrimeCell Identification Register 2

SMCPCellID3

0xFFC

RO

0xB1

See PrimeCell Identification Register 3

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