Table A.1 describes the common AMBA AHB signals.
Inverted bus clock input. It is used only for the generation of the write enable output.
Bus clock input, that times all bus transfers. All signal timings are related to the rising edge.
Bus reset input, active LOW, used to reset the system and the bus when asserted LOW.
Other AHB slaves
Transfer completed input. When HIGH the HREADYIN signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.