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A.3. AMBA AHB master interface signals

Table A.3 describes the AMBA AHB master interface signals.

AMBA AHB master interface signals

Signal name

Type

Source/ destination

Description

HRESPTIC[1:0]

Input

AMBA AHB slave

The transfer response provides additional information on the status of a transfer. The TIC supports both SPLIT and RETRY responses.

HRDATATIC[31:0]

Input

AMBA AHB slave

The read data bus is used to transfer data from bus slaves to the bus master during test read operations.

HGRANTTIC

Input

AMBA AHB arbiter

This signal indicates that the TIC is currently the highest priority master. Ownership of the address or control signals changes at the end of the transfer when HREADYIN is HIGH.

HADDRTIC[31:0]

Output

AMBA AHB slave

The 32-bit system address bus.

HTRANSTIC[1:0]

Output

AMBA AHB slave

Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, or IDLE. The TIC does not use the BUSY transfer type.

HWRITETIC

Output

AMBA AHB slave

Transfer direction signal. When HIGH, this signal indicates a write to the PrimeCell AHB SMC and when LOW, a read from the PrimeCell AHB SMC block.

HSIZETIC[2:0]

Output

AMBA AHB slave

Transfer size signal. This signal indicates the size of the current transfer, which can be byte (8-bit), halfword (16-bit) or word (32-bit). The TIC does not support larger transfer sizes.

HBURSTTIC[2:0]

Output

AMBA AHB slave

Indicates if the transfer forms part of a burst. The TIC always performs incrementing bursts of unspecified length.

HPROTTIC[3:0]

Output

AMBA AHB slave

The protection control signals indicate if the transfer is an opcode fetch or data access, and if the transfer is a Supervisor mode access or User mode access. These signals can also indicate whether the current access is cacheable or unbufferable.

HWDATATIC[31:0]

Output

AMBA AHB slave

The write data bus is used to transfer data from the master to bus slaves during write operations. A minimum data bus width of 32 bits is recommended, however this can easily be extended to enable for higher bandwidth operation.

HBUSREQTIC

Output

AMBA AHB arbiter

A signal from the TIC to the bus arbiter that indicates that it requires the bus.

HLOCKTIC

Output

AMBA AHB arbiter

When HIGH this signal indicates that the TIC requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

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