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A.4. Internal signals

Table A.4 describes the internal signals.

Internal signal descriptions

Signal name

Type

Source/ destination

Description

BIGENDIAN

Input

System

This static configuration bit indicates the type of endianness of the memory system:

0 = little-endian

1 = big-endian.

EXTBUSMUX

Input

System

This static configuration bit indicates if the internal bus multiplexor (DBI) is used, or if an external bus multiplexor (for example EBI) is used instead:

0 = internal bus multiplexor

1 = external bus multiplexor

MCBUSREQ

Input

Additional memory controller

Bus request signal, indicates that the additional memory controller block has requested use of the external bus.

MCADDR[25:0]

Input

Additional memory controller

Address output to external bus.

MCDATAOUT[31:0]

Input

Additional memory controller

Data output, used to write data from the additional memory controller to the external data bus.

MCDATAEN[3:0]

Input

Additional memory controller

Tristate input/output pad enable for the byte lanes of the external memory data bus MCDATAOUT[31:0]. Enables the byte lanes [31:24], [23:16], [15:8], and [7:0] of the data bus independently.

MCBUSGNT

Output

Additional memory controller

Bus grant signal, indicates that the additional memory controller is granted control of the external bus.

SMBUSREQEBI

Output

External bus multiplexor

Bus request signal, indicates that the SMC has requested use of the external bus. Only used when EXTBUSMUX tied to one.

SMBUSGNTEBI

Input

External bus multiplexor

Bus grant signal, indicates that the SMC is granted control of the external bus. Only used when EXTBUSMUX tied to one.

TICBUSREQEBI

Output

External bus multiplexor

Bus request signal, indicates that the TIC has requested use of the external bus. Only used when EXTBUSMUX tied to one.

TICBUSGNTEBI

Input

External bus multiplexor

Bus grant signal, indicates that the TIC is granted control of the external bus. Only used when EXTBUSMUX tied to one.

TICREADEBI

Output

External bus multiplexor

Data bus enable for TBUSOUTEBI. Only used when EXTBUSMUX tied to one.

TBUSOUTEBI[31:0]

Output

External bus multiplexor

TIC data bus output used during reads from the external tester. Only used when EXTBUSMUX tied to one.

REMAP

Input

System

Indicates the state of the memory map:

0 = reset memory map (SMCS7 mapped to SMCS0)

1 = normal memory map.

SCANENABLE

Input

System

Dummy pin used as a dedicated scan enable input.

SCANINnHCLK

Input

System

Dummy pin used as a dedicated nHCLK scan chain input.

SCANINHCLK

Input

System

Dummy pin used as a dedicated HCLK scan chain input.

SCANOUTnHCLK

Output

System

Dummy pin used as a dedicated nHCLK scan chain output.

SCANOUTHCLK

Output

System

Dummy pin used as a dedicated HCLK scan chain output.

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