The SMC is an AMBA AHB slave module that provides an interface between an AMBA AHB system bus and external (off-chip) memory devices.
The PrimeCell SMC provides support for up to eight independently configurable memory banks simultaneously. Each memory bank is capable of supporting:
burst ROM memory.
You can configure each memory bank to use either 8, 16, or 32-bit external memory data paths. The PrimeCell SMC can be configured to support either little-endian or big-endian operation.
The PrimeCell SMC memory banks can be configured to support:
nonburst read and write accesses to high-speed CMOS Static RAM, for example Samsung KM681002A and K6R1016C1C, and Intel 28F800C3
nonburst write accesses, nonburst read accesses, and asynchronous page mode read accesses to fast-boot block flash memory, for example Intel 28F800F3 and 28F128J3A
asynchronous page mode read accesses to ROM, for example Samsung K3P5V(U)2000D-SC and K3P6C2000B-SC.
Support is provided for connecting an additional AHB asynchronous memory controller to external memory, to pass the address, data and data enable lines to the external bus. A simple request and grant protocol is used to control the current driver of the external bus. Use of a synchronous memory controller is also supported, but this requires the use of a suitable external bus multiplexor. See Using the SMC with an external bus multiplexor or SDRAM controller for more details.
Figure 2.1 shows a block diagram of the PrimeCell SMC.
The three main sub-blocks in the PrimeCell SMC design are:
- SMC core
Performs read and write accesses to external memory through the AMBA AHB slave interface.
- Test interface controller
The TIC is used during testing to read external test vectors and apply them to the system through the AMBA AHB master interface.
- Data bus interface
The data bus interface selects either the memory controller, the TIC, or the additional memory controller as the current user of the external data bus.