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2.3. Memory bank selection

Eight independently configurable memory banks are supported, with a separate chip select output for each bank. The chip select lines SMCS[7:0] for all banks are configurable to be either active HIGH or active LOW (default). Table 2.1 shows how memory bank selection is controlled by the AMBA AHB address lines HADDR[28:26]. All SMCS lines are shown as active HIGH.

Static memory bank select coding

HADDR [28:26]

SMCS[7:0]

Memory bank

000

00000001

Bank 0

001

00000010

Bank 1

010

00000100

Bank 2

011

00001000

Bank 3

100

00010000

Bank 4

101

00100000

Bank 5

110

01000000

Bank 6

111

10000000

Bank 7

The base addresses of the external memory banks and the PrimeCell SMC memory bank registers are defined in the AMBA AHB address decoder. This generates the AHB slave select signals HSELSMC and HSELREG. If the default base address of the external memory banks begins at 0x00000000, the memory banks occupy address space up to 0x1FFFFFFF (8x64MB).

Table 2.2 shows the address mapping of HADDR[31:0] for external memory banks and for memory bank Configuration Registers.

HADDR[31:0] address mapping
HADDR[31:0][31:29] [1][28:26][25:12][11:2][1:0]
External memory banks

Base address for PrimeCell SMC memory

Chip select address space for eight memory banks

64MB memory banks address space

Memory bank Configuration RegistersBase address for PrimeCell AHB SMC registersUnusedUnused

Memory bank register select

Unused

[1] HADDR[31:29] are not inputs to the SMC. Decoding is performed in the AMBA address decoder.

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