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1.5. Additional asynchronous memory controller

Figure 1.4 shows the signal connections of an additional asynchronous memory controller to the PrimeCell SMC.

Figure 1.4. Signal connections for additional asynchronous memory controller

Figure 1.4. Signal connections for additional
asynchronous memory controller

Depending on the bus request and grant protocol supported by the additional memory controller, a simple wrapper might be required to enable it to operate with the protocol implemented in the PrimeCell SMC.

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