The following applies to the registers used in the PrimeCell SMC:
The base addresses for the PrimeCell SMC bank configuration registers and memory banks can be configured to suit each particular system implementation.
The base addresses must be configured by constant definitions in the Hardware Description Language (HDL) code for the AMBA address decoder.
The base addresses are not software-programmable. The PrimeCell SMC registers and memory banks have fixed address offsets from the base addresses described above.
Reserved or unused address locations must not be accessed because this can result in unpredictable behavior of the device.
Reserved or unused bits of registers must be written as zero, and ignored on read unless otherwise stated in the relevant text.
All register bits are reset to a logic 0 by a system or power-on reset unless otherwise stated in the relevant text.
All registers support read and write accesses unless otherwise stated in the relevant text. A write updates the contents of a register and a read returns the contents of the register.