If the core is in debug state (see Debug state), you can execute any CP14 debug instruction regardless of the processor mode.
If the processor tries to execute a CP14 debug instruction that either is not in Table 13.28, or is targeted to a reserved register, such as a non-implemented BVR, the Undefined instruction exception is taken.
You can access the DCC (read DIDR, read DSCR and read/write DTR) in User mode. All other CP14 debug instructions are privileged. If the processor tries to execute one of these in User mode, the Undefined instruction exception is taken.
If the User mode access to DCC disable bit, DSCR, is set, all CP14 debug instructions are considered as privileged, and all attempted User mode accesses to CP14 debug registers generate an Undefined instruction exception.
When DSCR bit 14 is set (Halt mode selected and enabled), if the software running on the processor tries to access any register other than the DIDR, the DSCR, or the DTR, the core takes the Undefined instruction exception. The same thing happens if the core is not in any debug mode (DSCR[15:14]=b00).
This lockout mechanism ensures that the software running on the core cannot modify the settings of a debug event programmed by the DBGTAP debugger.
Table 13.29 shows the results of executing CP14 debug instructions.
|State when executing CP14 debug instruction:||Results of CP14 debug instruction execution:|
|Processor mode||Debug state||DSCR[15:14] (Mode enabled and selected)||DSCR (DCC User accesses disabled)||Read DIDR, read DSCR and read/ write DTR||Write DSCR||Read/write other registers|
|User||No||xx||0||Proceed||Undefined exception||Undefined exception|
|User||No||xx||1||Undefined exception||Undefined exception||Undefined exception|
|Privileged||No||b00 (None)||x||Proceed||Proceed||Undefined exception|
|Privileged||No||b01 (Halt)||x||Proceed||Proceed||Undefined exception|
|Privileged||No||b11 (Halt)||x||Proceed||Proceed||Undefined exception|