The ARM1136JF-S processor has an external debug request input signal, EDBGRQ. When this signal is HIGH it causes the processor to enter debug state when execution of the current instruction has completed. When this happens, the DSCR[5:2] method of entry bits are set to b0100.
This signal can be driven by the ETM to signal a trigger to the core. For example, if the processor is in Halt mode and a memory permission fault occurs, an external trace analyzer can collect trace information around this trigger event at the same time that the processor is stopped to examine its state. See the Chapter 15 Trace Interface Port for more details. A DBGTAP debugger can also drive this signal.