When a Software debug event occurs and Monitor debug-mode is selected and enabled then a Debug exception is taken. Prefetch Abort and Data Abort Vector catch debug events are ignored though. Unlinked context ID breakpoint debug events are also ignored if the processor is running in a privileged mode and Monitor debug-mode is selected and enabled.
If the cause of the Debug exception is a watchpoint debug event, the processor performs the following actions:
The DSCR[5:2] method of entry bits are set to indicate that a watchpoint occurred.
The CP15 DFSR, FAR, and WFAR, are set as described in Effect of a debug event on CP15 registers.
The same sequence of actions as in a Data Abort exception is performed. This includes setting the r14_abt, base register and destination registers to the same values as if this was a Data Abort.
The Data Abort handler is responsible for checking the DFSR or DSCR[5:2] bit to determine if the routine entry was caused by a debug exception or a Data Abort exception. On entry:
It must first check for the presence of a monitor target.
If present, the handler must disable the active watchpoints. This is necessary to prevent corruption of the DFSR because of an unexpected watchpoint debug event while servicing a Data Abort exception.
If the cause is a Debug exception the Data Abort handler branches to the monitor target.
The FAR is set to an Unpredictable value.
The address of the instruction that caused the watchpoint debug event can be found in the WFAR.
The address of the instruction to restart at plus
0x08can be found in the r14_abt register.
If the cause of the Debug exception is a breakpoint, software breakpoint or vector catch debug event, the processor performs the following actions:
the DSCR[5:2] method of entry bits are set appropriately
the CP15 IFSR register is set as described in Effect of a debug event on CP15 registers
the same sequence of actions as in a Prefetch Abort exception is performed.
The Prefetch Abort handler is responsible for checking the IFSR or DSCR[5:2] bits to find out if the routine entry is caused by a Debug exception or a Prefetch Abort exception. If the cause is a Debug exception it branches to the monitor target.
The address of the instruction causing the Software debug
0x04 can be found in the r14_abt register.
Table 13.32 shows the values in the link register after exceptions.
|Cause of the fault||ARM||Thumb||Java||Return address (RA) meaning|
|Breakpoint||RA+4||RA+4||RA+4||Breakpointed instruction address|
|Watchpoint||RA+8||RA+8||RA+8||Address of the instruction where the execution resumes (a number of instructions after the one that hit the watchpoint)|
|BKPT instruction||RA+4||RA+4||RA+4||BKPT instruction address|
|Vector catch||RA+4||RA+4||RA+4||Vector address|
|Prefetch Abort||RA+4||RA+4||RA+4||Address of the instruction where the execution resumes|
|Data Abort||RA+8||RA+8||RA+8||Address of the instruction where the execution resumes|
 This is the address of the first instruction the processor must executes on return from handling the debug event.
 With the ARM1136JF-S processor, watchpoints are imprecise. RA might not be the address of the instruction that follows the one that hit the watchpoint, because the processor might stop a number of instructions later. The address of the instruction that hit the watchpoint is in the CP15 WFAR.