Debugging must be non-intrusive in a cached system. In ARM1136JF-S systems, you can preserve the contents of the cache so the state of the target application is not altered, and to maintain memory coherency during debugging.
To preserve the contents of the level one cache, you can disable the Instruction Cache and Data Cache line fills so read misses from main memory do not update the caches. You can put the caches in this mode by programming the operation of the caches during debug using CP15 c15. See c15, Cache Debug Control Register. This facility is accessible from both the core and DBGTAP debugger sides.
In debug state, the caches behave as follows, for memory coherency purposes:
Cache reads behave as for normal operation.
Writes are covered in Data Cache writes.
ARMv6 includes CP15 instructions for cleaning and invalidating the cache content, See c7, Cache Operations Register. These instructions enable you to reset the processor memory system to a known safe state, and are accessible from both the core and the DBGTAP debugger side.