Debugging in a system with TLBs has to be as non-intrusive as possible. There has to be a way to put the TLBs in a state where their contents are not affected by the debugging process. This facility has to be accessible from both the core and the DBGTAP debugger side. The ARM1136JF-S processor enables you to put the TLBs in this mode using CP15 c15. See Control of main TLB and MicroTLB loading and matching .
The ARM1136JF-S processor also enables you to read the state of the MicroTLBs and Main TLB with no side effects. This facility is accessible through CP15 c15 operations. See c15, MMU debug operations overview for more details.