Halt mode is used to debug the ARM1136JF-S processor using external hardware connected to the DBGTAP. The external hardware provides an interface to a DBGTAP debugger application. You can only select Halt mode by setting the halt bit (bit 14) of the DSCR, which is only writable through the Debug Test Access Port. See Chapter 14 Debug Test Access Port.
In Halt mode the processor stops executing instructions if one of the following events occurs:
a breakpoint hits
a watchpoint hits
a BKPT instruction is executed
the EDBGRQ signal is asserted
a Halt instruction has been scanned into the DBGTAP Instruction Register
a vector catch occurs.
When the processor is halted, it is controlled by sending instructions to the integer unit through the DBGTAP. Any valid instruction can be scanned into the processor, and the effect of the instruction upon the integer unit is as if it was executed under normal operation. Also accessible through the DBGTAP is a register to transfer data between CP14 and the DBGTAP debugger.
The integer unit is restarted by executing a DBGTAP Restart instruction.
From the r1p0 release, the system performance monitoring does not count any event while the processor is in debug halt mode. This means that the following counters are not incremented while in halt mode: