The level two memory interface exists to provide a high-bandwidth interface to second level caches, on-chip RAM, peripherals, and interfaces to external memory.
It is a key feature in ensuring high system performance, providing a higher bandwidth mechanism for filling the caches in a cache miss than has existed on previous ARM processors.
The ARM1136JF-S processor level two interconnect system uses the following 64-bit wide AHB-Lite interfaces:
Instruction Fetch Interface
Data Read Interface
Data Write Interface
Another interface is also provided. The Peripheral Interface is a 32-bit AHB-Lite interface.
The level two interconnect interfaces are shown in Figure 8.1.
These interfaces provide for several simultaneous outstanding transactions, giving the potential for high performance from level two memory systems that support parallelism, and also for high utilization of pipelined memories such as SDRAM.
Each of the four wide interfaces is an AHB-Lite interface, with additional signals to support additional features for the level two memory system:
shared memory synchronization primitives
multi-level cache support
unaligned and mixed-endian data access.