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8.4. Instruction Fetch Interface AHB-Lite transfers

The tables in this section describe the AHB-Lite interface behavior for instruction side fetches to either Cachable or Noncachable regions of memory for the following interface signals:

  • HBURSTI[2:0]

  • HTRANSI[1:0]

  • HADDRI[31:0]

  • HBSTRBI[7:0]


See Other AHB-Lite signals for Cachable and Noncachable instruction fetches for details of the other AHB-Lite signals.

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