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8.2. Synchronization primitives

On previous architectures support for shared memory synchronization has been with the read-locked-write operations that swap register contents with memory, the SWP and SWPB instructions. These support basic busy and free semaphore mechanisms. For details of the swap instructions, and how to use them to implement semaphores, see the ARM Architecture Reference Manual.

ARMv6 and ARMv6k describe support for more comprehensive shared-memory synchronization primitives that scale for multiple-processor system designs. Instructions are introduced that support multiple-processor and shared-memory inter-process communication:

  • load exclusive, LDREX

  • store exclusive, STREX

  • load byte exclusive, LDREXB

  • store byte exclusive, STREXB

  • load halfword exclusive, LDREXH

  • store halfword exclusive, STREXH

  • load doubleword exclusive, LDREXD

  • store doubleword exclusive, STREXD

  • clear exclusive, CLREX


The ARMv6k architecture features were introduce in the rev1 (r1p0) release of the ARM1136JF-S processor. This means that the LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX instructions are only available from the rev1 (r1p0) release of the processor.

The exclusive access instructions rely on the ability to tag a physical address as exclusive access for a particular processor. This tag is later used to determine if an exclusive store to an address occurs.

For memory regions that have the Shared TLB attribute, any attempt to modify that address by any processor clears this tag.

For memory regions that do not have the Shared TLB attribute, any attempt to modify that address by the same processor that marked it as exclusive access clears this tag.

In both cases other events might cause the tag to be cleared. In particular, for memory regions that are not shared, it is Unpredictable whether a store by another processor to a tagged physical address causes the tag to be cleared.


All exclusive transactions must be a single access, or an indivisible burst if the bus width is less than 64 bits.

An External Abort on any load exclusive or store exclusive instruction puts the processor into Abort mode.


An External Abort on any load exclusive instruction can leave the ARM1136JF-S internal monitor in its exclusive state and might affect your software. If it does you must ensure that a CLREX is executed in your abort handler to clear the ARM1136JF-S internal monitor to an open state.

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