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6.11.1. Backwards-compatible page table translation (subpage AP bits enabled)

When the CP15 Control Register c1 bit 23 is set to 0, the subpage AP bits are enabled and the page table formats are backwards-compatible with ARMv4 and ARMv5 MMU architectures.

All mappings are treated as global, and executable (XN = 0). All Normal memory is Non-Shared. Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits.

For large and small pages, there can be four subpages defined with different access permissions. For a large page, the subpage size is 16KB and is accessed using bits [15:14] of the page index of the Virtual Address. For a small page, the subpage size is 1KB and is accessed using bits [11:10] of the page index of the Virtual Address.

The use of subpage AP bits where AP3, AP2, AP1, and AP0 contain different values is deprecated.

Backwards-compatible page table format

Figure 6.4 shows a backwards-compatible format first-level descriptor.

Figure 6.4. Backwards-compatible first-level descriptor format

Figure 6.4. Backwards-compatible first-level
descriptor format

If the P bit is supported and set for the memory region, it indicates to the system memory controller that this memory region has ECC enabled.

Figure 6.5 shows a backwards-compatible format second-level descriptor for a page table.

Figure 6.5. Backwards-compatible second-level descriptor format

Figure 6.5. Backwards-compatible second-level
descriptor format

For extended small page table entries without a TEX field you must use the value b000.

For details of TEX encodings see C and B bit, and type extension field encodings.

Figure 6.6 shows an overview of the section, supersection, and page translation process using backwards-compatible descriptors.

Figure 6.6. Backwards-compatible section, supersection, and page translation

Figure 6.6. Backwards-compatible section, supersection,
and page translation
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