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6.11.3. Restrictions on page table mappings (page coloring)

The ARM1136JF-S processor uses virtually indexed, physically addressed caches. To prevent alias problems where cache sizes greater than 16KB have been implemented, you must restrict the mapping of pages that remap Virtual Address bits [13:12]. Bit[11] and bit[23] in the CP15 c0 Cache Type Register, the P bits for the instruction and data caches, indicate if this restriction is necessary (see c0, Cache Type Register and Figure 3.11).

This restriction, referred to as page coloring, enables these bits of the Virtual Address to be used to index into the cache without requiring hardware support to avoid alias problems. For pages marked as Non-Shared, if bit 11 or bit 23 of the Cache Type Register is set, the restriction applies to pages that remap Virtual Address bits [13:12] and might cause aliasing problems when 4KB pages are used. To prevent this you must ensure the following restrictions are applied:

  1. If multiple Virtual Addresses are mapped onto the same physical address then for all mappings, bits [13:12] of the Virtual Addresses must be equal and the same as bits [13:12] of the physical address. Imposing this requirement on the virtual addresses is sometimes called page coloring.

    The same physical address can be mapped by TLB entries of different page sizes, including page sizes over 4KB.

  2. Alternatively, if all mappings to a physical address are of a page size equal to 4KB, then the restriction that bits[13:12] of the Virtual Address must equal bits[13:12] of the physical address is not necessary. Bits[13:12] of all Virtual Address aliases must still be equal.

There is no restriction on the more significant bits in the Virtual Address equalling those in the physical address.

Avoiding the page coloring restriction

From release r1p0 of the ARM1136JF-S processor, the page coloring restriction can be removed by setting the CZ flag (bit[6]) in the CP15 Auxiliary Control Register, see c1, Auxiliary Control Register. If you set this flag, the sizes of the data and instruction caches will be restricted to 16KB.

Note

Setting the CZ flag in the CP15 Auxiliary Control Register does not affect the contents of the CP15 Cache Type Register. However, when the CZ flag is set all caches will be limited to 16KB, even if a larger cache size is specified in the CP15 Cache Type Register.

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