During the processing of a section or page, the MMU behaves differently because it is checking for faults. The MMU generates four types of fault:
Aborts that are detected by the MMU are taken before any external memory access takes place.
Alignment fault checking is enabled by the A bit in the Control Register CP15 c1. Alignment fault checking is independent of the MMU being enabled. Translation, Access Flag, Domain, and Permission faults are only generated when the MMU is enabled.
The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is detected as the result of a memory access, the MMU aborts the access and signals the fault condition to the processor. The MMU retains status and address information about faults generated by data accesses in DFSR and FAR, see Fault status and address. The MMU does not retain status about faults generated by instruction fetches.
An access violation for a given memory access inhibits any corresponding external access, and an abort is returned to the ARM1136JF-S processor.