When the core decodes a coprocessor instruction destined for a different coprocessor to that last addressed, it stalls this instruction until the previous coprocessor instruction has been retired. This ensures that all activity in the currently selected coprocessor has ceased.
The coprocessor selection is switched, disabling the last active coprocessor and activating the new coprocessor. The coprocessor that should have received the new coprocessor instruction must have ignored it, being disabled. Therefore, the instruction is resent by the core, and is now accepted by the newly activated coprocessor.
A coprocessor is disabled by the core by setting ACPENABLE LOW for the selected coprocessor. The coprocessor responds by ceasing all activity and setting all its output signals LOW.
When the coprocessor is enabled, which is signaled by setting ACPENABLE HIGH, it must immediately set the signals CPALENGTHHOLD and CPAACCEPTHOLD HIGH, and CPASTDATAV LOW, because the pipeline is empty at this point. The coprocessor can then start normal operation.