You copied the Doc URL to your clipboard.

1.8.2. Thumb instruction set summary

The Thumb instruction set summary is given in Table 1.15.

Thumb instruction set summary
Operation Assembler
MoveImmediate, update flagsMOV <Rd>, #<immed_8>
LowReg to LowReg, update flagsMOV <Rd>, <Rm>
HighReg to LowRegMOV <Rd>, <Rm>
LowReg to HighRegMOV <Rd>, <Rm>
HighReg to HighRegMOV <Rd>, <Rm>
ArithmeticAddADD <Rd>, <Rn>, #<immed_3>
Add immediateADD <Rd>, #<immed_8>
Add LowReg and LowReg, update flagsADD <Rd>, <Rn>, <Rm>
Add HighReg to LowRegADD <Rd>, <Rm>
Add LowReg to HighRegADD <Rd>, <Rm>
Add HighReg to HighRegADD <Rd>, <Rm>
Add immediate to PCADD <Rd>, PC, #<immed_8*4>
Add immediate to SPADD <Rd>, SP, #<immed_8*4>
Add immediate to SP

ADD SP, #<immed_7*4>

ADD SP, SP, #<immed_7*4>

Add with carryADC <Rd>, <Rs>
Subtract immediateSUB <Rd>, <Rn>, #<immed_3>
Subtract immediateSUB <Rd>, #<immed_8>
SubtractSUB <Rd>, <Rn>, <Rm>
Subtract immediateSUB SP, #<immed_8>
Subtract immediate from SPSUB <Rd>, #<immed_7*4>
Subtract with carrySBC <Rd>, <Rm>
NegateNEG <Rd>, <Rm>
MultiplyMUL <Rd>, <Rm>
CompareCompare immediateCMP <Rn>, #<immed_8>
Compare LowReg and LowReg, update flagsCMP <Rn>, <Rm>
Compare LowReg and HighRegCMP <Rn>, <Rm>
Compare HighReg and LowRegCMP <Rn>, <Rm>
Compare HighReg and HighRegCMP <Rn>, <Rm>
Compare negativeCMN <Rn>, <Rm>
LogicalANDAND <Rd>, <Rm>
XOREOR <Rd>, <Rm>
ORORR <Rd>, <Rm>
Bit clearBIC <Rd>, <Rm>
Move NOTMVN <Rd>, <Rm>
Test bitsTST <Rd>, <Rm>
Shift/RotateLogical shift left

LSL <Rd>, <Rm>, #<immed_5>

LSL <Rd>, <Rs>

Logical shift right

LSR <Rd>, <Rm>, #<immed_5>

LSR <Rd>, <Rs>

Arithmetic shift right

ASR <Rd>, <Rm>, #<immed_5>

ASR <Rd>, <Rs>

Rotate rightROR <Rd>, <Rs>
BranchConditionalB{cond} <label>
UnconditionalB <label>
Branch with linkBL <label>

Branch, link and exchange

BLX <label>

Branch, link and exchange

BLX <Rm>
Branch and exchangeBX <Rm>
LoadWith immediate offset-
 WordLDR <Rd>, [<Rn>, #<immed_5>]
 HalfwordLDRH <Rd>, [<Rn>, #<immed_5*2>]
 ByteLDRB <Rd>, [<Rn>, #<immed_5*4>]
With register offset-
 WordLDR <Rd>, [<Rn>, <Rm>]
 HalfwordLDRH <Rd>, [<Rn>, <Rm>]
 Signed halfwordLDRSH <Rd>, [<Rn>, <Rm>]
 ByteLDRB <Rd>, [<Rn>, <Rm>]
 Signed byteLDRSB <Rd>, [<Rn>, <Rm>]
 PC-relativeLDR <Rd>, [PC, #<immed_8*4>]
 SP-relativeLDR <Rd>, [SP, #<immed_8*4>]
 MultipleLDMIA <Rn>!, <reglist>
StoreWith immediate offset-
 WordSTR <Rd>, [<Rn>, #<immed_5*4>]
 HalfwordSTRH <Rd>, [<Rn>, #<immed_5*2>]
 ByteSTRB <Rd>, [<Rn>, #<immed_5>]
With register offset-
 WordSTR <Rd>, [<Rn>, <Rm>]
 HalfwordSTRH <Rd>, [<Rn>, <Rm>]
 ByteSTRB <Rd>, [<Rn>, <Rm>]
 SP-relativeSTR <Rd>, [SP, #<immed_8*4>]
 MultipleSTMIA <Rn>!, <reglist>
Push/PopPush registers onto stackPUSH <reglist>
Push LR and registers onto stackPUSH <reglist, LR>
Pop registers from stackPOP <reglist>
Pop registers and PC from stackPOP <reglist, PC>
Change stateChange processor stateCPS <effect> <iflags>
Change endiannessSETEND <endian_specifier>
Byte-reverseByte-reverse word REV <Rd>, <Rm>
Byte-reverse halfwordREV16 <Rd>, <Rm>
Byte-reverse signed halfwordREVSH <Rd>, <Rm>
Software interrupt  SWI <immed_8>
Software breakpoint  BKPT <immed_8>
Sign or zero extendSign extend 16 to 32SEXT16 <Rd>, <Rm>
Sign extend 8 to 32SEXT8 <Rd>, <Rm>
Zero extend 16 to 32UEXT16 <Rd>, <Rm>
Zero extend 8 to 32UEXT8 <Rd>, <Rm>
Was this page helpful? Yes No