Table 1.3 shows the ARM1136JF-S processor configurable options.
|Feature||Range of options|
|Cache way size||1KB, 2KB, 4KB, 8KB, or 16KB|
|TCM block size||0KB, 4KB, 8KB, 16KB, 32KB, or 64KB|
The number of TCM blocks and the number of TCM blocks supporting SmartCache are restricted to a minimum to reduce the impact on performance.
In addition, the form of the BIST solution for the RAM blocks in the ARM1136JF-S design is determined when the processor is implemented. For details, see the ARM1136JF-S and ARM1136J-S Implementation Guide.
Table 1.4 shows the default configuration of ARM1136JF-S processor.