Figure 1.2 shows:
the two Fetch stages
a Decode stage
an Issue stage
the four stages of the ARM1136JF-S integer execution pipeline.
These eight stages make up the ARM1136JF-S pipeline.
The pipeline stages are:
First stage of instruction fetch and branch prediction.
Second stage of instruction fetch and branch prediction.
Register read and instruction issue.
Main integer operation calculation.
Pipeline stage to enable saturation of integer results.
Write back of data from the multiply or main execution pipelines.
First stage of the multiply-accumulate pipeline.
Second stage of the multiply-accumulate pipeline.
Third stage of the multiply-accumulate pipeline.
Address generation stage.
First stage of Data Cache access.
Second stage of Data Cache access.
Write back of data from the Load Store Unit.
By overlapping the various stages of operation, the ARM1136JF-S processor maximizes the clock rate achievable to execute each instruction. It delivers a throughput approaching one instruction for each cycle.
The Fetch stages can hold up to four instructions, where branch prediction is performed on instructions ahead of execution of earlier instructions.
The Issue and Decode stages can contain any instruction in parallel with a predicted branch.
The Execute, Memory, and Write stages can contain a predicted branch, an ALU or multiply instruction, a load/store multiple instruction, and a coprocessor instruction in parallel execution.