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1.5. Pipeline stages

Figure 1.2 shows:

  • the two Fetch stages

  • a Decode stage

  • an Issue stage

  • the four stages of the ARM1136JF-S integer execution pipeline.

These eight stages make up the ARM1136JF-S pipeline.

Figure 1.2. ARM1136JF-S pipeline stages

Figure 1.2. ARM1136JF-S pipeline stages

The pipeline stages are:

Fe1

First stage of instruction fetch and branch prediction.

Fe2

Second stage of instruction fetch and branch prediction.

De

Instruction decode.

Iss

Register read and instruction issue.

Sh

Shifter stage.

ALU

Main integer operation calculation.

Sat

Pipeline stage to enable saturation of integer results.

WBex

Write back of data from the multiply or main execution pipelines.

MAC1

First stage of the multiply-accumulate pipeline.

MAC2

Second stage of the multiply-accumulate pipeline.

MAC3

Third stage of the multiply-accumulate pipeline.

ADD

Address generation stage.

DC1

First stage of Data Cache access.

DC2

Second stage of Data Cache access.

WBls

Write back of data from the Load Store Unit.

By overlapping the various stages of operation, the ARM1136JF-S processor maximizes the clock rate achievable to execute each instruction. It delivers a throughput approaching one instruction for each cycle.

The Fetch stages can hold up to four instructions, where branch prediction is performed on instructions ahead of execution of earlier instructions.

The Issue and Decode stages can contain any instruction in parallel with a predicted branch.

The Execute, Memory, and Write stages can contain a predicted branch, an ALU or multiply instruction, a load/store multiple instruction, and a coprocessor instruction in parallel execution.

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