The ARM1136JF-S processor includes several micro-architectural features to reduce energy consumption:
Accurate branch and return prediction, reducing the number of incorrect instruction fetch and decode operations.
Use of physically tagged caches, which reduce the number of cache flushes and refills, to save energy in the system.
The use of MicroTLBs reduces the power consumed in translation and protection look-ups for each memory access.
The caches use sequential access information to reduce the number of accesses to the TagRAMs and to unmatched data RAMs.
Extensive use of gated clocks and gates to disable inputs to unused functional blocks. Because of this, only the logic actively in use to perform a calculation consumes any dynamic power.
The ARM1136JF-S processor support four levels of power management:
- Run mode
This mode is the normal mode of operation in which all of the functionality of the ARM1136JF-S processor is available.
- Standby mode
This mode disables most of the clocks of the device, while keeping the device powered up. This reduces the power drawn to the static leakage current, plus a tiny clock power overhead required to enable the device to wake up from the standby state. The transition from the standby mode to the run mode is caused by one of the following:
an interrupt, either masked or unmasked
a debug request, regardless of whether debug is enabled
- Shutdown mode
This mode has the entire device powered down. All state, including cache and TCM state, must be saved externally. The part is returned to the run state by the assertion of reset. This state saving is performed with interrupts disabled, and finishes with a Drain Write Buffer operation. The ARM1136JF-S processor then communicates with the power controller that it is ready to be powered down.
- Dormant mode
This mode enables the ARM1136JF-S processor to be powered down, while leaving the state of the caches and the TCM powered up and maintaining their state. Although software visibility of the valid bits is provided to enable implementation of dormant mode, the following are required for full implementation of dormant mode:
modification of the RAMs to include an input clamp
implementation of separate power domains.
Power management features are described in more detail in Chapter 10 Power Control.