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1.9. Product revisions

This is the Technical Reference Manual for ARM1136J-S and ARM1136JF-S processors. This section summarizes the differences in functionality between the releases of these processors.

r0p0 - r1p0

The r1p0 release includes some significant changes in architecture and functionality, to provide ARM v6k support. These changes are described in Appendix B Functional changes in the rev1 (r1p0 to r1p3) releases. In summary, this release:

  • Adds new byte, halfword and double word exclusive instructions.

  • Adds new CLREX and true NOP instructions.

  • Adds two new CP15 MMU remap registers, and provides an additional TEX remapping option.

  • Adds new CP15 thread and process ID registers.

  • Changes the MMU access permission encodings.

  • Adds the ability to limit the apparent size of the implemented caches. This allows you to avoid the ARMv6 software page coloring restriction.

  • Allows you to redefine AP[0] for use as a software-controlled Access Flag, and provides a TLB-generated Access Flag fault.

  • Adds a set of feature registers to coprocessor 15 register 0.

r1p0 - r1p1

Maintenance upgrade to fix errata. No changes to the functionality described in this TRM.

r1p1- r1p3

Non-technical update. No changes to the functionality described in this TRM.

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