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1.6. Typical pipeline operations

Figure 1.3 shows all the operations in each of the pipeline stages in the ALU pipeline, the load/store pipeline, and the HUM buffers.

Figure 1.3. Typical operations in pipeline stages

Figure 1.3. Typical operations in pipeline stages

Figure 1.4 shows a typical ALU data processing instruction. The processor does not use the load/store pipeline or the HUM buffer are not used.

Figure 1.4. Pipeline for a typical ALU operation

Figure 1.4. Pipeline for a typical ALU operation

Figure 1.5 shows a typical multiply operation. The MUL instruction can loop in the MAC1 stage until it has passed through the first part of the multiplier array enough times. Then it progresses to MAC2 and MAC3 where it passes once through the second half of the array to produce the final result.

Figure 1.5. Pipeline for a typical multiply operation

Figure 1.5. Pipeline for a typical multiply operation
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