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6.10. Fault status and address

The encodings for the Fault Status Register are shown in Table 6.13.

Fault Status Register encoding
PrioritySourcesFSR[10,3:0]DomainFAR
HighestAlignmentb00001InvalidValid
 Cache maintenance[1] operation faultb00100InvalidValid
 External abort on translationFirst-levelb01100InvalidValid
  Second-levelb01110ValidValid
 TranslationSectionb00101InvalidValid
  Pageb00111ValidValid
 Access Flag fault[2]Sectionb00011[3]ValidValid
  Pageb00110[3]ValidValid
 DomainSectionb01001ValidValid
  Pageb01011ValidValid
 PermissionSectionb01101ValidValid
  Pageb01111ValidValid
 Precise External Abort b01000ValidValid
 Imprecise External Abortb10110InvalidInvalid
LowestDebug eventb00010ValidInvalid

[1] These aborts cannot be signaled with the IFSR because they do not occur on the instruction side.

[2] These aborts can only occur if enabled by setting the AFE bit, bit[29], in the CP15 Control Register, see c1, Control Register. In addition, the AFE bit is only considered if the XP bit, bit[23], in the CP15 control register is set (ARMv6 mode). Access Flag Faults are only defined from the rev1 (r1p0) release of the ARM1136JF-S processor, and these FSR encodings are reserved in rev0 RTL releases.

[3] Because of the limited encoding space for FSR encodings, the Access Flag fault encodings do not follow the Section/Page encoding pattern used for the other TLB-generated faults. However, the Access Flag fault encodings are consistent with the other TLB-generated faults in only using four bits (FSR[3:0]) for their encoding.

Note

All other Fault Status Register encodings are reserved.

Note

The b00011 encoding has been used previously for the Alignment fault. This is very unlikely to cause a problem, because the ARM memory model has changed considerably since that use was deprecated.

If a translation abort occurs during a Data Cache maintenance operation by Virtual Address, then a Data Abort is taken and the DFSR indicates the reason. The FAR indicates the faulting address.

If a translation abort occurs during an Instruction cache maintenance operation by Virtual Address, then a Data Abort is taken, and an Instruction cache maintenance operation fault is indicated in the DFSR. The FAR indicates the faulting address.

Domain and fault address information is only available for data accesses. For instruction aborts r14 must be used to determine the faulting address. You can determine the domain information by performing a TLB lookup for the faulting address and extracting the domain field.

A summary of which abort vector is taken, and which of the Fault Status and Fault Address Registers are updated for each abort type is shown in Table 6.14.

Summary of aborts
Abort typeAbort takenPrecise?Register updated?
IFSRWFARDFSRFAR
Instruction MMU faultPrefetch AbortYesYesNoNoNo
Instruction debug abortPrefetch AbortYesYesNoNoNo
Instruction External Abort on translationPrefetch AbortYesYesNoNoNo
Instruction External AbortPrefetch AbortYesYesNoNoNo
Memory barrier maintenance operationData AbortYesYesYes[1]YesYes
Data MMU faultData AbortYesNoYes[1]YesYes
Data debug abortData AbortNoNoYesYesYes[2]
Data External Abort on translationData AbortYesNoYes[1]YesYes
Data External AbortData AbortNo[3]NoNoYesNo
Data cache maintenance operationData AbortYesNoYes[1]YesYes

[1] Although the WFAR is updated by the processor the behavior is architecturally Unpredictable.

[2] The processor updates the FAR with an Unpredictable value.

[3] Data Aborts can be precise, see External aborts for more details.