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2.9.7. The control bits

The bottom eight bits of a PSR are known collectively as the control bits. They are the:

The control bits change when an exception occurs. When the processor is operating in a privileged mode, software can manipulate these bits.

Interrupt disable bits

The I and F bits are the interrupt disable bits:

  • when the I bit is set, IRQ interrupts are disabled

  • when the F bit is set, FIQ interrupts are disabled.

T bit

The T bit reflects the operating state:

  • when the T bit is set, the processor is executing in Thumb state

  • when the T bit is clear, the processor is executing in ARM state, or Java state depending on the J bit.

Note

Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If an MSR instruction does try to modify this bit the result is architecturally Unpredictable. In the ARM1136JF-S processor this bit is not affected.

Mode bits

An illegal value programmed into M[4:0] causes the processor to enter an unrecoverable state. If this occurs, you must apply reset. Not all combinations of the mode bits define a valid processor mode, so take care to use only those bit combinations shown.

Table 2.4 shows the M[4:0] mode bits that are used to determine the processor operating mode.

PSR mode bit values

M[4:0]

Mode

Visible state registers

Thumb

ARM

b10000

User

r0–r7, r8-r12[1], SP, LR, PC, CPSR

r0–r14, PC, CPSR

b10001

FIQ

r0–r7, r8_fiq-r12_fiq[1], SP_fiq, LR_fiq PC, CPSR, SPSR_fiq

r0–r7, r8_fiq–r14_fiq, PC, CPSR, SPSR_fiq

b10010

IRQ

r0–r7, r8-r12[1], SP_irq, LR_irq, PC, CPSR, SPSR_irq

r0–r12, r13_irq, r14_irq, PC, CPSR, SPSR_irq

b10011

Supervisor

r0–r7, r8-r12[1], SP_svc, LR_svc, PC, CPSR, SPSR_svc

r0–r12, r13_svc, r14_svc, PC, CPSR, SPSR_svc

b10111

Abort

r0–r7, r8-r12[1], SP_abt, LR_abt, PC, CPSR, SPSR_abt

r0–r12, r13_abt, r14_abt, PC, CPSR, SPSR_abt

b11011

Undefined

r0–r7, r8-r12[1], SP_und, LR_und, PC, CPSR, SPSR_und

r0–r12, r13_und, r14_und, PC, CPSR, SPSR_und

b11111

System

r0–r7, r8-r12[1], SP, LR, PC, CPSR

r0–r14, PC, CPSR

[1] Access to these registers is limited in Thumb state.

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