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3.3.47. MMU debugging

The debug architecture for the ARM1136JF-S processor is described in Chapter 13 Debug. The External Debug Interface is based on JTAG, and is described in Chapter 14 Debug Test Access Port.

In this section:

  • MicroTLB debug describes the sequence of CP15 c15 operations needed to debug the MicroTLBs

  • Main TLB debug describes the sequence of CP15 c15 operations needed to debug the main TLBs.

MicroTLB debug

You can use the debugger to read MicroTLB entries using CP15 c15 operations to specify the index in the MicroTLB to determine which entry you want to read, and then using further CP15 c15 operations to read the required values.

Note

It is possible for the microTLBs to be updated during this process. In this case the returned results will be a mixture of values from two microTLB entries. To avoid this possibility, you should disable microTLB load and flush before performing a debug read of the required microTLB.

The process for reliable debug access to the microTLBs is:

  • Disable microTLB load and flush by setting the appropriate bit of the TLB Debug Control Register, bit[1] for instruction microTLBs, bit[0] for data microTLBs. See Control of main TLB and MicroTLB loading and matching for more information.

  • Specify the microTLB entry you want to read by writing the microTLB index number to the Instruction microTLB Index Register or the Data microTLB Index Register.

  • Read the contents of the microTLB from these registers:

    • MicroTLB VA Register

    • MicroTLB PA Register

    • MicroTLB Attributes Register.

  • When you have finished debugging, re-enable normal operation of the microTLBs by clearing the appropriate bit in the TLB Debug Control Register.

The format of the VA, PA, and Attributes registers for the main TLB and MicroTLB entries are described in:

This mechanism cannot be used to write the microTLB entries. The debugger cannot write microTLB entries.

Main TLB debug

The debugger can read or write the individual entries of the main TLB using CP15 c15 operations that specify the index of the main TLB entry to be written or read. This enables a debugger to determine the individual entries within the main TLB. When a Read Main TLB Entry Register command is issued the operation reads the requested main TLB entry into the following registers:

  • Main TLB VA Register

  • Main TLB PA Register

  • Main TLB Attributes Register.

In a similar manner, a Write Main TLB Entry Register operation copies these registers into the main TLB.

The format of the VA, PA, and Attributes registers for the main TLB and MicroTLB entries are described in:

Control of main TLB and MicroTLB loading and matching

You can disable the MicroTLB automatic loading from the main TLB, the loading of the main TLB after a hardware page table walk, and the matching of entries in either the main TLB or the MicroTLB using the TLB Debug Control Register in CP15 c15.

When the automatic loading from the MicroTLB is disabled, all MicroTLB misses are serviced from the main TLB, and do not update the MicroTLB. When the loading of the main TLB is disabled, then misses do not result in the main TLB being updated. This has a significant impact on performance, but enables debug operations to be performed in as unobtrusive a manner as possible.

Disabling matches:

  • in the MicroTLB causes all accesses to be serviced from the main TLB

  • in the main TLB causes all accesses to be serviced by doing a page table walk.

This enables alternative page mappings to be created without having to change the TLB contents. This enables debugging to be performed in as unobtrusive a manner as possible. Disabling matches without also disabling the loading of the corresponding TLB can have Unpredictable effects.