This section describes alignment faults and the operation of non-faulting accesses of the ARM1136JF-S processor.
The mechanism for the support of unaligned loads or stores is as follows:
if either the Base register or the index offset of the address is misaligned, then:
the processor takes two cycles to issue the instruction
if the resulting address is misaligned, then the instruction performs multiple memory accesses in ascending order of address.
There is no support for misaligned accesses being atomic, and misaligned accesses to Device memory might result in Unpredictable behavior.
Table 4.3 gives details of when an Alignment fault must occur for an access, and of when the behavior of an access is architecturally Unpredictable. When an access does not generate an Alignment fault and is not Unpredictable, the table gives details of precisely which memory locations are accessed.
|Access type||ARM instructions||Thumb instructions|
|Byte||LDRB, LDRBT, LDRSB, STRB, STRBT, SWPB (either access)||LDRB, LDRSB, STRB|
|BSync||SWPB, LDREXB, STREXB||–|
|Halfword||LDRH, LDRSH, STRH||LDRH, LDRSH, STRH|
|WLoad||LDR, LDRT, SWP (load access, if U is set to 0)||LDR|
|WStore||STR, STRT, SWP (store access, if U is set to 0)||STR|
|WSync||LDREX, STREX, SWP (either access, if U is set to 1)||–|
|Multi-word||LDC, LDM, RFE, SRS, STC, STM||LDMIA, POP, PUSH, STMIA|
 The LDREXB, LDREXH, LDREXD, STREXB, STREXH, and STREXD instructions are only available from the rev1 (r1p0) release of the ARM1136JF-S processor. The BSync, HWSync and DWSync access types are only defined from the rev1 (r1p0) release.
The following terminology is used to describe the memory locations accessed:
This means the byte whose address is X in the current endianness model. The correspondence between the endianness models is that Byte[A] in the LE endianness model, Byte[A] in the BE-8 endianness model, and Byte[A EOR 3] in the BE-32 endianness model are the same actual byte of memory.
This means the halfword consisting of the bytes whose addresses are X and X+1 in the current endianness model, combined to form a halfword in little-endian order in the LE endianness model or in big-endian order in the BE-8 or BE-32 endianness model.
This means the word consisting of the bytes whose addresses are X, X+1, X+2, and X+3 in the current endianness model, combined to form a word in little-endian order in the LE endianness model or in big-endian order in the BE-8 or BE-32 endianness model.
These definitions mean that, if X is word-aligned, Word[X] consists of the same four bytes of actual memory in the same order in the LE and BE-32 endianness models.
This means X AND
0xFFFFFFFC. That is, X with its least significant two bits forced to zero to make it word-aligned.
On lines where Addr[1:0] is set to b00 there is no difference between Addr and Align(Addr). You can use this to simplify the control of when the least significant bits are forced to zero.
For the Two-word and Multi-word access types, the memory accessed column only specifies the lowest word accessed. Subsequent words have addresses constructed by successively incrementing the address of the lowest word by four, and are constructed using the same endianness model as the lowest word.
|A||U||Addr [2:0]||Access type(s)||Architectural behavior||Memory accessed||Notes|
|0||0||–||–||–||–||Legacy, no alignment faulting|
|0||0||bxx1||Halfword||Unpredictable||–||Halfword[Align16(Addr)]; Operation unaffected by Addr|
|0||0||bxx1||HWSync||Unpredictable||–||Halfword[Align16(Addr)]; Operation unaffected by Addr|
|0||0||bxxx||WLoad||Normal||Word[Align32(Addr)]||Loaded data rotated right by 8 * Addr[1:0] bits|
|0||0||bxxx||WStore||Normal||Word[Align32(Addr)]||Operation unaffected by Addr[1:0]|
|0||0||bxx1, b x1x||WSync||Unpredictable||–||Word[Align32(Addr)]|
|0||0||bxxx||Multi-word||Normal||Word[Align32(Addr)]||Operation unaffected by Addr[1:0]|
|0||0||bxx1, bx1x, b1xx||Double-word||Unpredictable||–||Same as LDM2 or STM2|
|0||0||bxx1, bx1x, b1xx||DWSync||Unpredictable||–|
Operation unaffected by Addr[2:0]
|0||1||–||–||–||–||ARMv6 unaligned support|
|0||1||bx00||WSync, Multi-word, Double-word||Normal||Word[Addr]||–|
|0||1||bxx1, bx1x||WSync, Multi-word, Double-word||Alignment fault||–||–|
|0||1||bxx1, bx1x, b1xx||DWSync||Alignment fault||–||–|
|1||x||–||–||–||–||Full alignment faulting|
|1||x||bxx1||Halfword, HWSync||Alignment fault||–||–|
|1||x||bx00||WLoad, WStore, WSync, Multi-word||Normal||Word[Addr]||–|
|1||x||bxx1, b x1x||WLoad, WStore, WSync, Multi-word||Alignment fault||–||–|
|1||x||bxx1, bx1x||Double-word||Alignment fault||–||–|
|1||x||bxx1, bx1x, b1xx||DWSync||Alignment fault||–||–|
 The BSync, HWSync and DWSync access types are only defined from the rev1 (r1p0) release of the ARM1136JF-S processor.
The following causes override the behavior specified in the Table 4.3:
An LDR instruction that loads the PC, has Addr[1:0] != b00, and is specified in the table as having Normal behavior instead has Unpredictable behavior.
The reason why this applies only to LDR is that most other load instructions are Unpredictable regardless of alignment if the PC is specified as their destination register.
The exceptions are the ARM LDM and RFE instructions, and the Thumb POP instruction. If the instruction for them is Addr[1:0] != b00, the effective address of the transfer has its two least significant bits forced to 0 if A is set 0 and U is set to 0. Otherwise the behavior specified in Table 4.3 is either Unpredictable or an Alignment fault regardless of the destination register.
Any WLoad, WStore, WSync, Double-word, or Multi-word instruction that accesses device memory, has Addr[1:0] != b00, and is specified in Table 4.3 as having Normal behavior instead has Unpredictable behavior.
Any Halfword instruction that accesses device memory, has Addr != 0, and is specified in Table 4.3 as having Normal behavior instead has Unpredictable behavior.