Figure 12.1 shows the VIC port and the Peripheral Interface connecting a PL192 VIC and an ARM1136JF-S processor.
The VIC port enables the processor to read the vector address
as part of the IRQ interrupt entry. That is, the ARM1136JF-S processor
takes a vector address from this interface instead of using the
The VIC port does not support the reading of FIQ vector addresses.
The interrupt interface is designed to handle interrupts asserted by a controller that is clocked either synchronously or asynchronously to the ARM1136JF-S processor clock. This capability ensures that the controller can be used in systems that have either a synchronous or asynchronous interface between the core clock and the AHB clock.
The VIC port consists of the signals shown in Table 12.1.
|nFIQ||Input||Active LOW fast interrupt request signal|
|nIRQ||Input||Active LOW normal interrupt request signal|
|INTSYNCEN||Input||If this signal is asserted, the internal nFIQ and nIRQ synchronizers are bypassed|
|IRQADDRVSYNCEN||Input||If this signal is asserted, the internal IRQADDRV synchronizer is bypassed|
|IRQACK||Output||Active HIGH IRQ acknowledge|
|IRQADDRV||Input||Active HIGH valid signal for the IRQ interrupt vector address below|
|IRQADDR[31:2]||Input||IRQ interrupt vector address. IRQADDR[31:2] holds the address of the first ARM state instruction in the IRQ handler|
IRQACK is driven by the ARM1136JF-S processor to indicate to an external VIC that the processor wants to read the IRQADDR input.
IRQADDRV is driven by a VIC to tell the ARM1136JF-S processor that the address on the IRQADDR bus is valid and being held, and so it is safe for the processor to sample it.
IRQACK and IRQADDRV together implement a four-phase handshake between the ARM1136JF-S processor and a VIC. See Timing of the VIC port for more details.