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13.6.5. Effect of a debug event on CP15 registers

The four CP15 registers that can be set on a debug event are:

  • Instruction Fault Status Register (IFSR)

  • Data Fault Status Register (DFSR)

  • Fault Address Register (FAR)

  • Watchpoint Fault Address Register (WFAR).

They are set under the following circumstances:

  • The IFSR is set whenever a breakpoint, software breakpoint, or vector catch debug event generates a Debug exception entry. It is set to indicate the cause for the Prefetch Abort vector fetch.

  • The DFSR is set whenever a watchpoint debug event generates a Debug exception entry. It is set to indicate the cause for the Data Abort vector fetch.

  • The ARM1136JF-S processor sets the FAR to an Unpredictable value.

  • The WFAR is set whenever a watchpoint debug event generates either a Debug exception or Debug state entry. It is set to the VA of the instruction that caused the Watchpoint debug event, plus an offset dependent on the processor state. Table 13.33 shows the offsets that are used.

    Table 13.31 shows the setting of CP15 registers on debug events.

    Table 13.31. Setting of CP15 registers on debug events
    RegisterDebug exception taken due to:Debug state entry due to:
    A breakpoint, software breakpoint, or vector catch debug eventA watchpoint debug eventA debug event other than a watchpointA watchpoint debug event
    IFSRCause of Prefetch Abort exception handler entryUnchangedUnchangedUnchanged
    DFSRUnchangedCause of Data Abort exception handler entryUnchangedUnchanged
    FARUnchangedUnpredictable valueUnchangedUnchanged
    WFARUnchangedAddress of the instruction causing the watchpoint debug eventUnchangedAddress of the instruction causing the watchpoint debug event

You must take care when setting a breakpoint or software breakpoint debug event inside the Prefetch Abort or Data Abort exception handlers, or when setting a watchpoint debug event on a data address that might be accessed by any of these handlers. These debug events overwrite the R14_abt, SPRS_abt and the CP15 registers listed in this section, leading to an unpredictable software behavior if the handlers did not have the chance of saving the registers.