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13.3.3. CP14 c0, Debug ID Register (DIDR)

The purpose of the Debug ID Register (DIDR) is to define the configuration of the debug registers in the system.

The DIDR is:

Figure 13.3 shows the arrangement of bits in the register.

Figure 13.3. Debug ID Register format

Figure 13.3. Debug ID Register format

For the ARM1136JF-S r1p3 processor the value of the Debug ID Register is 0x1511xx13.

Table 13.4 shows the bit functions of the Debug ID Register.

Table 13.4. Debug ID Register bit field definitions
BitsNameAttributesFunctionValue
[31:28]WRPR

Number of Watchpoint Register Pairs. The number of pairs is one more than the value held in this field, so:

b0000 corresponds to 1 WRP,

b0001 corresponds to 2 WRPs,

up to b1111 for 16 WRPs.

The ARM1136JF-S processor has 2 WRPs.

b0001
[27: 24]BRPR

Number of Breakpoint Register Pairs. The number of pairs is one more than the value held in this field. The minimum number of pairs is two, and b0000 is Reserved. So:

b0001 corresponds to 2 BRPs,

b0010 corresponds to 3 BRPs,

up to b1111 for 16 BRPs.

The ARM1136JF-S processor has 6 BRPs.

b0101
[23: 20]ContextR

Number of Breakpoint Register Pairs with context ID comparison capability. The number of pairs is one more than the value held in this field, so:

b0000 corresponds to 1 BRP with context ID comparison capability,

b0001 corresponds to 2 BRPs with context ID comparison capability,

up to b1111 for 16 BRPs with context ID comparison capability.

The ARM1136JF-S processor has 2 BRPs with context ID comparison capability.

b0001
[19:16]VersionRDebug architecture version.b0001
[15:8]-UNP/SBZPReserved.-
[7: 4]VariantRImplementation-defined variant number. This number is incremented on functional changes.-[a]
[3: 0]RevisionRImplementation-defined revision number. This number is incremented on bug fixes.-[a]

[a] These values agree with values in the CP15 c0 Main ID Register, see the description in this section.


The values of the following fields of the Debug ID Register agree with the values in CP15 c0, Main ID Register:

  • DIDR[3:0] is the same as CP15 c0 bits [3:0]

  • DIDR[7:4] is the same as CP15 c0 bits [23:20].

See c0, Main ID Register for a description of CP15 c0, ID Register.

Note

The reason for duplicating these fields is that the Debug ID Register is accessible through scan chain 0. This enables an external debugger to determine the variant and revision numbers without stopping the core.

Accessing the Debug ID Register

Table 13.5 shows the results of attempted accesses to the Debug ID Register for each mode.

Table 13.5. Results of accesses to the Debug ID Register
Privileged readPrivileged writeUser read, DSCR[12][a]=0User read, DSCR[12][a]=1User write
Data readUndefined Instruction exceptionData readUndefined Instruction exceptionUndefined Instruction exception

[a] Bit[12] of the DSCR register, see CP14 c1, Debug Status and Control Register (DSCR). The value of this bit does not have any effect on any other mode of access to the Debug ID Register.


To access the Debug ID Register you read CP14 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c0

  • Opcode_2 set to 0.

For example:

MRC p14,0,<Rd>,c0,c0,0                ; Read Debug ID Register