The purpose of the Debug Status and Control Register (DSCR) is to:
provide status information about the state of the debug system
enable you to configure aspects of the debug system.
The DSCR is:
in CP14 c1
a 32-bit read/write register
fully accessible in privileged mode only:
If bit of the register is clear (0), the register can be read from User mode. However it is never possible to write to this register from User mode.
Figure 13.4 shows the arrangement of bits in the register.
Table 13.6 shows the bit functions of the Debug Status and Control Register.
|Bits||Field Name||Core view||External view||Function||Reset value|
Indicates the state of the DTR for read operations:
0 = rDTR empty
1 = rDTR full.
This flag is automatically set on writes by the DBGTAP debugger to the rDTR and is cleared on reads by the core of the same register. When the rDTRfull flag is set (1), no writes to the rDTR are enabled.
Indicates the state of the DTR for write operations:
0 = wDTR empty
1 = wDTR full.
This flag is automatically cleared on reads by the DBGTAP debugger of the wDTR and is set on writes by the core to the same register.
|||Monitor Mode Enable||RW||R|
This bit is used to enable Monitor debug-mode:
0 = Monitor debug-mode disabled
1 = Monitor debug-mode enabled.
For the core to take a debug exception, Monitor debug-mode has to be both selected and enabled (bit clear and bit set).
This bit is used to select Monitor debug-mode:
0 = Monitor debug-mode selected
1 = Halting debug-mode selected and enabled.
See the description of the Monitor Mode Enable bit, above.
This bit is used to enable the execution of ARM instructions:
0 = ARM instruction execution disabled
1 = ARM instruction execution enabled.
When this bit is set, the core can be forced to execute ARM instructions in Debug state using the Debug Test Access Port.
If this bit is set when the core is not in Debug state, the behavior of the ARM1136JF-S processor is Unpredictable.
This bit controls User mode access to the comms channel:
0 = User mode access to comms channel enabled
1 = User mode access to comms channel disabled.
If this bit is set and a User mode process tries to access the DIDR, DSCR, or the DTR, the Undefined Instruction exception is taken.[a]
This bit controls interrupts:
0 = Interrupts enabled
1 = Interrupts disabled.
When set, the IRQ and FIQ input signals are inhibited.[b]
0 = DBGNOPWRDWN is LOW
1 = DBGNOPWRDWN is HIGH.
See External signals.
|||Sticky imprecise aborts||R||RC|
This bit indicates that an imprecise Data Abort has occurred:
0 = No imprecise Data Aborts have occurred since the last time this bit was cleared
1 = An imprecise Data Abort has occurred since the last time this bit was cleared.
This bit is cleared on reads of a DBGTAP debugger to the DSCR.
|||Sticky precise abort||R||RC|
This bit indicates that a precise Data Abort has occurred:
0 = No precise Data Abort has occurred since the last time this bit was cleared
1 = A precise Data Abort has occurred since the last time this bit was cleared.
This bit is cleared on reads of a DBGTAP debugger to the DSCR.
This flag is provided to detect Data Aborts generated by instructions issued to the processor using the Debug Test Access Port. Therefore, if the DSCR execute ARM instruction enable bit is 0, the value of the sticky precise abort bit is Unpredictable.
|[5:2]||Entry||RW||R||This field shows the method of entry to Debug state. See Table 13.7 for the permitted values and their meaning.||b0000|
This bit enables a debugger to check whether the processor has exited from Debug state[c]:
0 = the processor is exiting Debug state
1 = the processor has exited Debug state.
See Exiting from Debug state for details of the use of this bit.
This bit indicates when the processor is in Debug state[c]:
0 = the processor is in normal state
1 = the processor is in Debug state.
After programming a debug event, the debugger polls this bit until it is set to 1 so it knows that the processor entered Debug state.
[a] Accessing other CP14 debug registers is never possible in User mode, see Executing CP14 debug instructions. This means that setting this bit means there is no User mode access to the CP14 debug registers.
[b] Bits[11:10] of this register (DSCR[11:10]) can be controlled by a DBGTAP debugger to execute code in normal state as part of the debugging process. For example, if the DBGTAP debugger has to execute an OS service to bring a page from disk into memory, and then return to the application to see the effect this change of state produces, ARM recommends that interrupts are not serviced during execution of this routine.
The Entry field in the DSCR shows how Debug state was entered. Table 13.7 gives the permitted values for this field.
|Entry value||Reason for entering debug|
|b0000||A Halt DBGTAP instruction occurred|
|b0001||A breakpoint occurred|
|b0010||A watchpoint occurred|
|b0100||A EDBGRQ signal activation occurred|
|b0101||A vector catch occurred|
|b0110||A data-side abort occurred|
|b0111||An instruction-side abort occurred|
The Entry field, bits[5:2] of the DSCR, indicates:
the reason for jumping to the Prefetch or Data Abort vector
the reason for entering Debug state.
A Prefetch Abort or a Data Abort handler will use these to determine if it must jump to the monitor target. Additionally, a DBGTAP debugger or monitor target can determine the specific debug event that caused the Debug state or debug exception entry.
The Core halted bit of the DSCR, DSCR, can be read to check whether the processor is in normal or Debug state. However, it might not be reliable for a debugger to use this bit to check for exit from Debug state. This is because another debug event could cause Debug state to be re-entered before the debugger has successfully polled DSCR to check for a return from Debug state. For this reason, the Core restarted bit, DSCR, is provided to enable reliable testing of exiting Debug state. An example of the use of DSCR illustrates this point.
After executing a DBGTAP IR instruction, the debugger polls the Core restarted bit until it is set to 1. At that point, the debugger knows that the IR instruction was effective, even if another debug event immediately causes re-entry to Debug state.
Figure 13.5 shows the relationship between the Core restarted bit and the Core halted bit. In this illustration, almost as soon as the core has been restarted a breakpoint causes it to re-enter Debug state. If the debugger was polling the Core restarted bit to check for exit from Debug state it might miss the return to normal state, and conclude that the IR instruction had failed. However, in the illustration, the fact that the Core restarted signal has been reset to HIGH confirms that the IR instruction was successful.
Table 13.5 shows the results of attempted accesses to the Debug Status and Control Register for each mode.
|Privileged read||Privileged write||User read, DSCR[a]=0||User read, DSCR[a]=1||User write|
|Data read||Data write[b]||Data read||Undefined Instruction exception||Undefined Instruction exception|
[a] Bit of the DSCR register. The value of this bit does not have any effect on any other mode of access to the Debug Status and Control Register.
To access the Debug Status and Control Register you read or write CP14 with:
Opcode_1 set to 0
CRn set to c0
CRm set to c1
Opcode_2 set to 0.
MRC p14,0,<Rd>,c0,c1,0 ; Read Debug Status and Control Register
MCR p14,0,<Rd>,c0,c1,0 ; Write Debug Status and Control Register