The purpose of the Watchpoint Control Registers (WCRs) is to contain the control bits needed for setting watchpoints and linked watchpoints.
The WCRs are:
in CP14 c112 - c113
two 32-bit read-write registers
only accessible in privileged mode, with debug monitor mode enabled.
Figure 13.12 shows the arrangement of bits in the registers.
Table 13.24 shows the bit functions of the Watchpoint Control Registers.
0 = Linking disabled
1 = Linking enabled.
When this bit is set, this watchpoint is linked with the BRP specified in bits[19:16], the Linked BRP field.
The binary number held in this field is the number of the BRP that is linked to this WRP. The linked BRP holds a Context ID to be used as part of the watchpoint definition.
Permitted values for this field are b0100 and b0101, corresponding to BRP4 and BRP5.
For more information see Breakpoint and watchpoint linking.
This field is ignored unless bit, the E bit, is set to 1.
|[8:5]||Byte address select||RW|
By default, watchpoint matching treats the address held in the WVR as a word address. You can use this field to program the watchpoint so it hits only if certain byte addresses are accessed.
Byte address selection is identical for the WVRs and the BVRs. See Using a byte address as a breakpoint or watchpoint for details.
Load or store access. You can use this field to make the watchpoint conditional on the type of access being made:
b00 = Reserved
b01 = Load
b10 = Store
b11 = Either.
See Watchpoints conditional on Load or Store operations for more information.
Supervisor Access. You can use this field to make the breakpoint conditional on the privilege of the access being made:
b00 = Reserved
b01 = Watchpoint only on privileged access
b10 = Watchpoint only on User access
b11 = Either. Watchpoint on any access.
0 = Watchpoint disabled
1 = Watchpoint enabled.
The watchpoint value contained in the WVR always corresponds to a DVA. Watchpoints can be set on:
a DVA/Context ID pair.
For the second case, you have to link the WRP to a BRP that holds a Context ID. This can only be BRP4 or BRP5. Linking a WRP to a BRP in this way, to specify a watchpoint that is conditional on both a DVA and a Context ID, is described in the section Breakpoint and watchpoint linking.
In addition to the rules for breakpoint debug event generation, see Breakpoint register operations, the following rules apply to watchpoint debug event generation with the ARM1136JF-S processor:
The update of a WVR or a WCR can take effect several instructions after the corresponding
MCR. It is only guaranteed to have taken effect by the next 1MB.
A WRP can be linked to a BRP that has Context ID comparison capability. Several BRPs (holding IVAs) and WRPs can be linked with the same context ID capable BRP.
BRP4 and BRP5 are the BRPs that have Context ID capability.
If a WRP is linked with a BRP that is not configured for Context ID comparison and linking, it is Unpredictable if a watchpoint debug event is generated or not. Whenever a WRP is linked to a BRP, the BCR[21:20] fields of the BRP must be set to b11.
If a WRP is linked with a BRP that is not implemented, it is Unpredictable if a watchpoint debug event is generated or not.
If a WRP is linked with a BRP and they are not both enabled, the WRP does not generate a watchpoint debug event.
The WRP and BRP are enabled by setting both BCR and WCR to 1.
The L/S field of a WCR, bits[4:3], can be used to make the watchpoint conditional on the type of access being made. Table 13.25 shows the permitted values for this field and their meanings.
|L/S field value||Meaning|
|b01||Watchpoint triggers on Load operations only.|
|b10||Watchpoint triggers on Store operations only.|
|b11||Either. Watchpoint triggers on all operations.|
Table 13.26 shows how the L/S field is interpreted for different operations.
|Operation||L/S field settings for Watchpoint to trigger|
|Load, Store or Either,|
|Load Exclusive, ||Load or Either.|
|Store Exclusive, |
Store or Either.
The watchpoint will trigger regardless of whether the command succeeded.
Table 13.27 shows the results of attempted accesses to the Watchpoint Control Registers for each mode.
|Privileged read,[a] DSCR[15:14][b]=b10||Privileged write,[a] DSCR[15:14][b]=b10||Privileged read or write, DSCR[15:14][b] !=b10||User read or write|
|Data read||Data write||Undefined Instruction exception||Undefined Instruction exception|
[a] These accesses are also possible when the processor is in Debug state.
To access the Watchpoint Control Registers you read or write CP14 with:
Opcode_1 set to 0
CRn set to c0
CRm set to the number of the WCR you want to access, either c0 for WCR0 or c1 for WCR1
Opcode_2 set to 7.
MRC p14, 0, <Rd>, c0, c1, 7 ; Read Watchpoint Control Register 1
MCR p14, 0, <Rd>, c0, c0, 7 ; Write Watchpoint Control Register 0