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13.3.5. CP14 c5, Data Transfer Registers (DTR)

The purpose of the Data Transfer Registers (DTRs) is to transfer data between the processor core and a DBGTAP debugger.

The DTRs are:

  • in CP14 c5

  • two 32-bit registers:

    • the read-only rDTR (Read Data Transfer Register)

    • the write-only wDTR (Write Data Transfer Register)

  • accessible in privileged mode, and accessible in User mode if bit[12] of the DSCR register is clear (0), see CP14 c1, Debug Status and Control Register (DSCR).

Note

Throughout the description of the DTR, read and write refer to the core view of the registers.

Which of the two physical registers is accessed depends on the instruction used:

  • writes, MCR and LDC instructions, access the wDTR

  • reads, MRC and STC instructions, access the rDTR.

For details of the use of these registers with the rDTRfull flag and wDTRfull flag see Debug communications channel. Figure 13.6 shows the arrangement of bits in the registers. This arrangement is the same for both the rDTR and the wDTR.

Figure 13.6. Data Transfer Registers format

Figure 13.6. Data Transfer Registers format

Table 13.9 shows the bit functions of the rDTR.

Table 13.9. Read Data Transfer Register bit field definitions
BitsCore viewExternal viewFunction
[31:0]RWRead data transfer register (read-only)

Table 13.10 shows the bit functions of the wDTR.

Table 13.10. Write Data Transfer Register bit field definitions
BitsCore viewExternal viewFunction
[31:0]WRWrite data transfer register (write-only)

Accessing the Data Transfer Registers

Table 13.5 shows the results of attempted accesses to the Data Transfer Registers for each mode.

Table 13.11. Results of accesses to the Data Transfer Registers
Privileged read[a]Privileged write[b]User read[a], DSCR[12][c]=0User write[b], DSCR[12][a]=0User read or write, DSCR[12][a]=1
Data readData writeData readData writeUndefined Instruction exception

[a] Read operations access the Read Data Transfer Register (rDTR).

[b] Write operations access the Write Data Transfer Register (wDTR).

[c] Bit[12] of the DSCR register, see CP14 c1, Debug Status and Control Register (DSCR). The value of this bit does not have any effect on privileged mode access to the Data Transfer Registers.


To access the Data Transfer Registers you read or write CP14 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c5

  • Opcode_2 set to 0.

For example:

MRC p14,0,<Rd>,c0,c5,0          ; Read the Read Data Transfer Register
MCR p14,0,<Rd>,c0,c5,0          ; Write the Write Data Transfer Register