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13.3.8. CP14 c64-c69, Breakpoint Value Registers (BVR)

The purpose of the Breakpoint Value Registers (BVRs) is to hold a IVA or Context ID value that is to be used as a breakpoint for debugging purposes.

The BVRs are:

  • in CP14 c64 - c69

  • six 32-bit read-write registers

  • only accessible in privileged mode, with debug monitor mode enabled.

The BVRs can only be used in conjunction with the Breakpoint Control Registers (BCRs), see CP14 c80-c85, Breakpoint Control Registers (BCR). Each BVR is associated with a BCR, to form a Breakpoint Register Pair (BRP). This pairing is described in Overview of breakpoint and watchpoint registers on the ARM1136JF-S processor.

Figure 13.8 shows the arrangement of bits in the Breakpoint Value Registers BVR0 to BVR3, and Figure 13.9 shows the arrangement for BVR4 and BVR5.

Figure 13.8. Breakpoint Value Registers BVR0 to BVR3 format

Figure 13.8. Breakpoint Value Registers BVR0 to
BVR3 format

Figure 13.9. Breakpoint Value Registers BVR4 and BVR5 format

Figure 13.9. Breakpoint Value Registers BVR4 and
BVR5 format

Table 13.15 shows the bit functions of the Breakpoint Value Registers BVR0 to BVR3, and Table 13.16 shows the bit functions of the Breakpoint Value Registers BVR4 and BVR5.

Table 13.15. Breakpoint Value Registers BVR0 to BVR3, bit field definitions
BitsAttributesFunction
[31:2]RWBreakpoint address (IVA)
[1:0]-Reserved, UNP/SBZP

Table 13.16. Breakpoint Value Registers BVR4 and BVR5, bit field definitions
BitsAttributesFunction
[31:0][a]RWBreakpoint address (IVA or Context ID)

[a] When the register is used for IVA comparison, bits[1:0] are ignored.


Because a BVR can only be used as part of a BRP, use of the BVRs is described in CP14 c80-c85, Breakpoint Control Registers (BCR).

Accessing the Breakpoint Value Registers

Table 13.17 shows the results of attempted accesses to the Breakpoint Value Registers for each mode.

Table 13.17. Results of accesses to the Breakpoint Value Registers
Privileged read,[a] DSCR[15:14][b]=b10Privileged write,[a] DSCR[15:14][b]=b10Privileged read or write, DSCR[15:14][b] !=b10User read or write
Data readData writeUndefined Instruction exceptionUndefined Instruction exception

[a] These accesses are also possible when the processor is in Debug state.

[b] Bits[15:14] of the DSCR register, see CP14 c1, Debug Status and Control Register (DSCR). Setting these bits to b10 enables debug monitor mode.


To access the Breakpoint Value Registers you read or write CP14 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to the number of the BVR you want to access, from c0 for BVR0 to c5 for BVR5

  • Opcode_2 set to 4.

For example:

MRC p14,0,<Rd>,c0,c1,4          ; Read Breakpoint Value Register 1
MCR p14,0,<Rd>,c0,c3,4          ; Write Breakpoint Value Register 3