The purpose of the Breakpoint Value Registers (BVRs) is to hold a IVA or Context ID value that is to be used as a breakpoint for debugging purposes.
The BVRs are:
in CP14 c64 - c69
six 32-bit read-write registers
only accessible in privileged mode, with debug monitor mode enabled.
The BVRs can only be used in conjunction with the Breakpoint Control Registers (BCRs), see CP14 c80-c85, Breakpoint Control Registers (BCR). Each BVR is associated with a BCR, to form a Breakpoint Register Pair (BRP). This pairing is described in Overview of breakpoint and watchpoint registers on the ARM1136JF-S processor.
|[31:2]||RW||Breakpoint address (IVA)|
Because a BVR can only be used as part of a BRP, use of the BVRs is described in CP14 c80-c85, Breakpoint Control Registers (BCR).
Table 13.17 shows the results of attempted accesses to the Breakpoint Value Registers for each mode.
|Privileged read,[a] DSCR[15:14][b]=b10||Privileged write,[a] DSCR[15:14][b]=b10||Privileged read or write, DSCR[15:14][b] !=b10||User read or write|
|Data read||Data write||Undefined Instruction exception||Undefined Instruction exception|
[a] These accesses are also possible when the processor is in Debug state.
To access the Breakpoint Value Registers you read or write CP14 with:
Opcode_1 set to 0
CRn set to c0
CRm set to the number of the BVR you want to access, from c0 for BVR0 to c5 for BVR5
Opcode_2 set to 4.
MRC p14,0,<Rd>,c0,c1,4 ; Read Breakpoint Value Register 1
MCR p14,0,<Rd>,c0,c3,4 ; Write Breakpoint Value Register 3