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13.3.6. CP14 c7, Vector Catch Register (VCR)

The purpose of the Vector Catch Register (VCR) is to enable vector catching. That is, to cause debug entry when a specified vector is committed for execution.

The VCR is:

  • in CP14 c7

  • a 32-bit read-write register

  • only accessible in privileged mode, with debug monitor mode enabled.

Figure 13.7 shows the arrangement of bits in the register.

Figure 13.7. Vector Catch Register format

Figure 13.7. Vector Catch Register format

Table 13.12 shows the bit field functions of the Vector Catch Register.

Table 13.12. Vector Catch Register bit field definitions
BitsAttributesDescriptionNormal addressHigh vector addressReset value
[31:8]-Reserved, UNP/SBZP---
[7]RWVector catch enable, FIQ0x0000001C0xFFFF001C0
[6]RWVector catch enable, IRQ

Most recent[a] IRQ address

Most recent[a] IRQ address0
[5]-Reserved, UNP/SBZP---
[4]RWVector catch enable, Data Abort0x000000100xFFFF00100
[3]RWVector catch enable, Prefetch Abort0x0000000C0xFFFF000C0
[2]RWVector catch enable, SWI0x000000080xFFFF00080
[1]RWVector catch enable, Undefined Instruction0x000000040xFFFF00040
[0]RWVector catch enable, Reset0x000000000xFFFF00000

[a] You can configure the ARM1136JF-S processor so that the IRQ uses vector exceptions other than 0x00000018 and 0xFFFF0018. See Changes to existing interrupt vectors for more details.


If one of the bits in this register is set and the corresponding vector is committed for execution, then a Debug exception or Debug state entry might be generated, depending on the value of the DSCR[15:14] bits (see Behavior of the processor on debug events). Under this model, any kind of fetch of an exception vector can trigger a vector catch, not just fetches due to exception entries.

Note

An update of the VCR might only occur several instruction after the corresponding MCR instruction. The update only takes effect by the next Instruction Memory Barrier (IMB).

Accessing the Vector Catch Register

Table 13.13 shows the results of attempted accesses to the Vector Catch Register for each mode.

Table 13.13. Results of accesses to the Vector Catch Register
Privileged read,[a] DSCR[15:14][b]=b10Privileged write,[a] DSCR[15:14][b]=b10Privileged read or write, DSCR[15:14][b] !=b10User read or write
Data readData writeUndefined Instruction exceptionUndefined Instruction exception

[a] These accesses are also possible when the processor is in Debug state.

[b] Bits[15:14] of the DSCR register, see CP14 c1, Debug Status and Control Register (DSCR). Setting these bits to b10 enables debug monitor mode.


To access the Vector Catch Register you read or write CP14 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c7

  • Opcode_2 set to 0.

For example:

MRC p14,0,<Rd>,c0,c7,0          ; Read the Vector Catch Register
MCR p14,0,<Rd>,c0,c7,0          ; Write the Vector Catch Register