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13.3.9. CP14 c80-c85, Breakpoint Control Registers (BCR)

The purpose of the Breakpoint Control Registers (BCRs) is to contain the control bits needed for setting breakpoints and linked breakpoints.

The BCRs are:

  • in CP14 c80 - c85

  • six 32-bit read-write registers

  • only accessible in privileged mode, with debug monitor mode enabled.

The BCRs can only be used in conjunction with the Breakpoint Value Registers (BVRs), see CP14 c64-c69, Breakpoint Value Registers (BVR). Each BCR is associated with a BVR, to form a Breakpoint Register Pair (BRP). This pairing is described in Overview of breakpoint and watchpoint registers on the ARM1136JF-S processor. The use of the BRPs is described later in this section.

Figure 13.10 shows the arrangement of bits in the registers.

Figure 13.10. Breakpoint Control Registers format

Figure 13.10. Breakpoint Control Registers format

Table 13.18 shows the bit functions of the Breakpoint Control Registers.

Table 13.18. Breakpoint Control Registers, bit field definitions
BitsNameAttributesFunctionReset value
[31:22]--Reserved, UNP/SBZP.-
[21]M[a]RW[a]

Meaning of the associated BVR[a]:

0 = The BVR holds an Instruction Virtual Address and is compared with the IVA bus.

1 = The BVR holds a Context ID and is compared with the CP15 Context ID Register.

For more information, see Table 13.20.

-
[20]ERW

Enable linking:

0 = Linking disabled.

1 = Linking enabled.

When this bit is set HIGH, the corresponding BRP is linked.

For more information, see Table 13.20.

-
[19:16]Linked BRPRW

The binary number held in this field is the number of another BRP to link this one with, see Breakpoint and watchpoint linkingfor details.

This field is only used when bits[21:20] of this register are set to b01. It is ignored for other values of bits[21:20].

Note

If bits[21:20]=b01 and this field links the BRP to itself, behavior is Unpredictable if a breakpoint debug event is generated.

-
[15:9] -Reserved, UNP/SBZP.-
[8:5]Byte address selectRW

By default, breakpoint matching treats the address held in the BVR as a word address. You can use this field to program the breakpoint so it hits only if certain byte addresses are accessed. See Using a byte address as a breakpoint or watchpoint for details.

This field must be set to b1111 if this BRP is programmed for Context ID comparison. See Breakpoints with a Context ID comparison for more information.

-
[4:3]--Reserved, UNP/SBZP.-
[2:1]SRW

Supervisor Access. You can use this field to make the breakpoint conditional on the privilege of the access being made:

b00 = Reserved.

b01= Breakpoint only on privileged access.

b10 = Breakpoint only on User access.

b11 = Either. Breakpoint on any access.

This field must be set to b11 if this BRP is linked and holds a Context ID. This means this field must be set to b11 if bits[21:20] are set to b11. See Breakpoint and watchpoint linking for more information.

-
[0]BRW

Breakpoint enable. This bit is used to enable or disable the breakpoint:

0 = Breakpoint disabled

1 = Breakpoint enabled.

0

[a] For registers BRC0 to BRC3, where the associated BVR is not context ID capable, the M field is not used and must be treated as UNP/SBZP.


Breakpoint register operations

The ARM1136JF-S processor supports thread-aware breakpoints and watchpoints. This means that breakpoints and watchpoints can be made conditional on the contents of the CP15 Context ID Register. The BRPs are used in the following ways:

  • a single BRP used to set a breakpoint on:

    • an IVA

    • a Context ID

  • two linked BRPs, to set a breakpoint on an IVA/context ID pair:

    • one BRP holds the required IVA

    • the second BRP holds the required Context ID

  • a BRP linked with a Watchpoint Register Pair (WRP), to set a watchpoint on a DVA/context ID pair:

    • the WRP holds the required watchpoint DVA

    • the BRP holds the required Context ID.

Whenever a BRP is used:

  • the BVR holds the required watchpoint IVA or context ID

  • the BCR specifies how the BRP is being used, including whether the BVR holds an IVA or a Context ID.

When a single BRP is used to set a breakpoint on an IVA, the contents of the BVR are compared with the IVA bus of the processor. When a match occurs, a breakpoint debug event is generated.

Breakpoint and watchpoint linking describes the linked BRP and BRP/WRP operations, and Breakpoints with a Context ID comparison gives more information about Context ID comparisons.

The following rules apply to the ARM1136JF-S processor for breakpoint debug event generation:

  • The update of a BVR or a BCR can take effect several instructions after the corresponding MCR. It takes effect by the next IMB.

  • Updates of the CP15 Context ID Register c13, can take effect several instructions after the corresponding MCR. However, the write takes place by the end of the exception return. This ensures that a User mode process, switched in by a processor scheduler, can break at its first instruction.

  • Any BRP (holding an IVA) can be linked to any other one with context ID capability. Several BRPs (holding IVAs) can be linked to the same context ID capable BRP.

  • If a BRP (holding an IVA) is linked with one that is not configured for context ID comparison and linking, it is Unpredictable whether a breakpoint debug event is generated or not.

    See Breakpoint and watchpoint linking for details of how the BCR[21:20] fields must be set when register pairs are linked.

  • If a BRP (holding an IVA) is linked with one that is not implemented, it is Unpredictable if a breakpoint debug event is generated or not.

  • If a BRP is linked with itself, it is Unpredictable if a breakpoint debug event is generated or not.

  • If a BRP (holding an IVA) is linked with another BRP (holding a context ID value), and they are not both enabled (both BCR[0] bits set), the first one does not generate any breakpoint debug events.

Using a byte address as a breakpoint or watchpoint

By default, IVA and DVA matching is performed on the word address held in the BVR or WVR. The rest of this section describes IVA matching against the BVR. However, byte address selection for DVA matching against the WVR is identical.

For this operation, the Byte address select field of the BCR (BCR[8:5]) is set to b1111, However, you can use this field to program the breakpoint so it hits only if certain byte addresses are accessed. This is shown in Table 13.19.

Table 13.19. Byte address select field values, bits[8:5], in the BCRs
Byte address select fieldBreakpoint hits
b0000Never.
bxxx1When the byte at address BVR[31:2]+0 is accessed.
bxx1xWhen the byte at address BVR[31:2]+1 is accessed.
bx1xxWhen the byte at address BVR[31:2]+2 is accessed.
b1xxxWhen the byte at address BVR[31:2]+3 is accessed.
b1111

When the word at address BVR[31:2] is accessed.

This is the default IVA matching.


The byte addresses in Table 13.19 are little-endian. This ensures that a breakpoint is triggered regardless of the endianness of the instruction fetch. For example, if a breakpoint is set on a certain Thumb instruction by setting BCR[8:5] = b0011, the breakpoint is triggered in both of these cases:

  • the fetch is little-endian and IVA[1:0] is b00

  • the fetch is big-endian and IVA[1:0] is b10.

Note

The Byte address select field is still used when a BVR is being used for Context ID comparison. Therefore, the field must be set to b1111 when a BRP is programmed for context ID comparison. Otherwise breakpoint or watchpoint debug events might not be generated as expected. This means that whenever BCR[21] is set to 1, to enable Context ID comparison, BCR[8:5] must be set to b1111.

Breakpoint and watchpoint linking

As indicated in Breakpoint register operations, there are two cases where BRPs are linked:

  • two BRPs are linked, to define a breakpoint conditional on a Context ID:

    • one BRP holds the required Context ID

    • the second BRP holds the required IVA

  • a BRP is linked to a WRP, to define a watchpoint conditional on a Context ID:

    • the BRP holds the required Context ID

    • the WRP holds the DVA for the watchpoint.

In both cases, two bits of the BCR must be set correctly to configure the linking; these are:

  • BCR[21], the M (Meaning) bit. This bit configures whether the associated BVR is being used for IVA matching (=0) or for Context ID matching (=1).

  • BCR[20], the E (Enable linking) bit. This bit configures whether BRP linking is disabled (=0) or enabled (=1).

Table 13.20 summarizes the meaning of BCR bits[21:20].

Table 13.20. Meaning of BCR[21:20] bits in a BCR
BCR[21:20]Meaning
b00The associated BVR is compared with the IVA bus. This BRP is not linked with any other one. It generates a breakpoint debug event on an IVA match.
b01

The associated BVR is compared with the IVA bus. This BRP is linked with the BRP indicated by the Linked BRP field, BCR[19:16] of this BCR. A breakpoint debug event is generated based on both:

  • matching the associated BVR with the IVA bus

  • matching the contents of the linked BVR with the Context ID.

b10The associated BVR is compared with the CP15 Context Id Register, c13. This BRP is not linked with any other one. It generates a breakpoint debug event on a context ID match.
b11

The associated BVR is compared with the CP15 Context Id Register, c13. Another BRP (of the BCR[21:20]=b01 type), or WRP (with WCR[20]=b1), is linked with this BRP. A breakpoint or watchpoint debug event is generated based on both:

  • matching the associated BVR with the Context ID

  • matching the linked BVR or WVR with the IVA or DVA bus.


Whenever you want to make a breakpoint or a watchpoint conditional on the Context ID, you link the BRP or WRP containing the required IVA or DVA to a BRP that contains the required Context ID. If you want to set up multiple breakpoints or watchpoints conditional on a single Context ID you can link multiple BRPs and WRPs to a single BRP that holds the required Context ID.

Remember that only BRP4 and BRP5 can be used to hold Context IDs.

See Setting breakpoints, watchpoints, and vector catch debug events for detailed programming sequences for linked breakpoints and linked watchpoints.

Privilege level conditions with breakpoint or watchpoint linking

Bits[2:1] of the BCR or of the WCR, the S field, enable you to make the breakpoint or watchpoint conditional on the privilege level (User or privileged) of the access being made. If you want to apply an access mode condition to a breakpoint or watchpoint that links a BRP or WRP to a BRP holding a context ID you must take particular care over the S field values:

  • The S field value (bits[2:1]) of the BRP or WRP holding the breakpoint or watchpoint match address take precedence over the S field of the BRP holding the Context ID. The S field of the BRP or WRP holding the match address must be set to the required privilege level of the breakpoint or watchpoint.

  • The S field of the BRP holding the Context ID must be set to b11 = either. This is because, where breakpoints or watchpoints are linked it is Undefined whether the S field of the BRP holding the Context ID is included in the comparison.

Summary of defining a breakpoint conditional on a Context ID

One BRP must be set up to specify the required Context ID. This must be BRP4 or BRP5. If this BRP is not already set up you must:

  • Program the BVR with the required Context ID.

  • In the associated BCR:

    • Set bit[21], the M bit, to 1, to specify that the BVR holds a Context ID.

    • Set bit[20], the E bit, to 1, to specify that this BRP is linked.

    • Set bits[8:5], the Byte address select field, to b1111, to ensure that all bytes of the BVR are used for Context ID matching.

    • Set bits[2:1], the S field, to b11. See Privilege level conditions with breakpoint or watchpoint linking for an explanation of this setting.

    • Set bit[0], the B field, to 1, to enable the breakpoint.

You must set up the second BRP to specify the required IVA:

  • Program the BVR with the required IVA.

  • In the associated BCR:

    • Set bit[21], the M bit, to 0, to specify that the BVR holds an IVA.

    • Set bit[20], the E bit, to 1, to specify that this BRP is linked to a second BRP.

    • Set bits[19:16], the Linked BRP field, to indicate the number of the BRP that holds the required Context ID. This field will be b100 or b101, for BRP4 or BRP5.

    • Set the Byte address select and S fields of the register if required, see Table 13.18 for more information.

    • Set bit[0], the B bit, to 1, to enable the breakpoint.

Summary of defining a watchpoint conditional on a Context ID

This is described here because it requires a BRP to hold the required Context ID. See CP14 c112-c113, Watchpoint Control Registers (WCR) for more information about defining watchpoints.

A BRP must be set up to specify the required Context ID. This must be BRP4 or BRP5. If this BRP is not already set up you must:

  • Program the BVR with the required Context ID.

  • In the associated BCR:

    • Set bit[21], the M bit, to 1, to specify that the BVR holds a Context ID.

    • Set bit[20], the E bit, to 1, to specify that this BRP is linked.

    • Set bits[8:5], the Byte address select field, to b1111, to ensure that all bytes of the BVR are used for Context ID matching.

    • Set bits[2:1], the S field, to b11. See Privilege level conditions with breakpoint or watchpoint linking for an explanation of this setting.

    • Set bit[0], the B field, to 1, to enable the breakpoint.

You must also set up a WRP to specify the required DVA:

  • Program the WVR with the required DVA.

  • In the associated WCR:

    • Set bit[20], the E bit, to 1, to specify that this WRP is linked to a BRP that holds a Context ID.

    • Set bits[19:16], the Linked BRP field, to indicate the number of the BRP that holds the required Context ID. This field will be b100 or b101, for BRP4 or BRP5.

    • Set the Byte address select, L/S and S fields of the register if required, see Table 13.24 for more information.

    • Set bit[0], the W bit, to 1, to enable the watchpoint.

Breakpoints with a Context ID comparison

This section contains additional information about setting breakpoints that involve a context ID comparison. The section Breakpoint and watchpoint linking described setting a breakpoint, or a watchpoint, based on a combination of a Context ID match with an IVA or DVA match. In these cases, a breakpoint or watchpoint debug event is only generated if both the address and the context ID match at the same time. This means that unnecessary hits can be avoided when debugging a specific thread within a task.

Breakpoint debug events generated on context ID matches only are also supported. However, if the match occurs while the processor is running in a privileged mode and the debug logic is in Monitor debug-mode, it is ignored. This is to avoid the processor ending in an unrecoverable state.

Context ID matches are based on comparing the value held in a BVR with the value held in the CP15 Context ID Register, see c13, Context ID Register. The contents of the BVR are compared with the Context ID Register whenever bit[21], the M (Meaning) bit of the associated BCR is set to 1.

Note

The Byte address select field of the BCR, BCR[8:5], is still used when the BVR is used for Context ID comparisons. You must set this field to b1111 whenever you configure a BRP for Context ID matching, to ensure the breakpoint or watchpoint debug events are generated correctly.

The S field of the BCR, BCR[2:1], is also applied to all Context ID comparisons. You will normally set this field to b11 when the associated BVR holds a Context ID. You must set this field to b11 when the Context ID comparison is linked to another BRP or WRP, see Privilege level conditions with breakpoint or watchpoint linking for more information.

Accessing the Breakpoint Control Registers

Table 13.17 shows the results of attempted accesses to the Breakpoint Control Registers for each mode.

Table 13.21. Results of accesses to the Breakpoint Control Registers
Privileged read,[a] DSCR[15:14][b]=b10Privileged write,[a] DSCR[15:14][b]=b10Privileged read or write, DSCR[15:14][b] !=b10User read or write
Data readData writeUndefined Instruction exceptionUndefined Instruction exception

[a] These accesses are also possible when the processor is in Debug state.

[b] Bits[15:14] of the DSCR register, see CP14 c1, Debug Status and Control Register (DSCR). Setting these bits to b10 enables debug monitor mode.


To access the Breakpoint Control Registers you read or write CP14 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to the number of the BCR you want to access, from c0 for BCR0 to c5 for BCR5

  • Opcode_2 set to 5.

For example:

MRC p14,0,<Rd>,c0,c1,5          ; Read Breakpoint Control Register 1
MCR p14,0,<Rd>,c0,c3,5          ; Write Breakpoint Control Register 3