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13.3.2. Debug register descriptions

Table 13.2 lists definitions of terms used in register descriptions.

Table 13.2. Terms used in register descriptions

Read-only. Written values are ignored. However, you must write these bits as 0 or preserve them by writing back the value previously read from the same field on the same processor.


Write-only. This bit cannot be read. Reads return an Unpredictable value.

RWRead or write.

Cleared on read. This bit is cleared whenever the register is read.


Unpredictable or Should Be Zero or Preserved (SBZP). A read to this bit returns an Unpredictable value. It is written as 0 or preserved by writing the same value previously read from the same fields on the same processor. These bits are usually reserved for future expansion.

Core view

This column defines the core access permission for a given bit.

External view

This column defines the DBGTAP debugger view of a given bit.


This is used when the core and the DBGTAP debugger view are the same.

On a power-on reset, all the CP14 debug registers take the values indicated by the Reset value column in the register bit field definition tables. In these tables, a hyphen (-) means an Undefined reset value.

Table 13.3. List of CP14 debug registers
Register nameAbbreviationReference to description
Debug ID RegisterDIDRSee CP14 c0, Debug ID Register (DIDR)
Debug Status and Control RegisterDSCRSee CP14 c1, Debug Status and Control Register (DSCR)
Data Transfer RegisterDTRSee CP14 c5, Data Transfer Registers (DTR)
Vector Catch RegisterVCRSee CP14 c7, Vector Catch Register (VCR)
Breakpoint Value RegistersBVRy[a]See CP14 c64-c69, Breakpoint Value Registers (BVR)
Breakpoint Control RegistersBCRy[a]See CP14 c80-c85, Breakpoint Control Registers (BCR)
Watchpoint Value Registers WVRy[a]See CP14 c96-c97, Watchpoint Value Registers (WVR)
Watchpoint Control Registers WCRy[a]See CP14 c112-c113, Watchpoint Control Registers (WCR)

[a] y is the register number; see the footnote to Table 13.1 for more details.